Abstract: The present invention relates to new coating compositions for the preparation of functional surface coatings on various base material substrates. The coating compositions are based on a silazane-containing polymer and a non-polymeric phenolic compound comprising at least two and not more than four aromatic units in its molecular structure. The coating compositions provide improved physical and chemical surface properties and may be applied by user-friendly coating methods.

Abstract: The present invention relates to new coating compositions for the preparation of functional surface coatings on various base material substrates. The coating compositions are based on a silazane-containing polymer and a non-polymeric phenolic compound comprising at least two and not more than four aromatic units in its molecular structure. The coating compositions provide improved physical and chemical surface properties and may be applied by user-friendly coating methods.

Abstract: Some embodiments relate to a method and a corresponding apparatus for estimating the wear of a non-volatile memory. Such a method may include determining a load profile with respect to a real access load occurring during a defined test period where the load profile indicates a respectively associated access load for accesses to a first NVM, and generating access data representing the determined load profile. The method further includes determining an estimated value for the wear of a particular second NVM in part on the basis of the access data.

Abstract: Some embodiments relate to a method and a corresponding apparatus for estimating the wear of a non-volatile memory. Such a method may include determining a load profile with respect to a real access load occurring during a defined test period where the load profile indicates a respectively associated access load for accesses to a first NVM, and generating access data representing the determined load profile. The method further includes determining an estimated value for the wear of a particular second NVM in part on the basis of the access data.

Abstract: Various embodiments are related to non-volatile memories, systems, and methods of using such. Some such embodiments include a memory controller that is configured to reserve a predetermined amount of unused dedicated memory in the NVM and control the memory system to operate in a normal mode of operation in which it is configured to provide at least write access to the NVM, enable a garbage collection process for the NVM, and maintain in the NVM at least said amount of dedicated unused memory. Reserving the predetermined amount of unused dedicated memory in the NVM and controlling the memory system to operate in the normal mode of operation includes reserving at least one specific unused dedicated memory portion in the NVM and controlling the memory system such that during the normal mode of operation the host's write access to the dedicated memory portion is disabled.

Abstract: Various embodiments are related to non-volatile memories, systems, and methods of using such.

Abstract: Embodiments are related to controlling a non-volatile digital information memory, such as a flash memory, by means of a memory controller. More specifically, embodiments are related to a method of controlling the information memory, a computer program being configured to perform the method, a memory controller for performing the method, and/or a memory system comprising such a memory controller.

Abstract: A method renews data in a flash memory which is organized in memory units and whose memory units which have been written to are error-protected using ECC words. The memory units which have been written to are test-read in regularly activated test-reading cycles, and either individual memory units which have been written to or all memory units which have been written to are renewed on the basis of the ECC error states which have occurred in a test-reading cycle.

Abstract: Extended commands are transmitted from computer system via a standard interface to a memory system. The computer system accesses logical memory addresses via an application interface using standard read/write commands which are processed by a memory controller in the memory system. A sequence of read commands for at least two logical memory addresses with address values that differ in at least one bit are output by the computer system. The memory controller compares the sequence of different bits with a predefined bit sequence, the magical address sequence. In the event of a match, a subsequent write command for one of the logical memory addresses is used to open a management connection between the computer system and the memory controller, and the useful data contained in the write command are evaluated by the memory controller and are not written to the addressed memory address.

Abstract: A flash memory for a host system has a multiplicity of memory blocks. The memory blocks are subdivided into memory pages which can be written to and each memory page are also subdivided into partial pages and each partial page having a physical partial page address which is assigned a logical partial page address which can be addressed. The physical partial page addresses assigned to the logical partial page addresses are able to be determined using hierarchically organized structures of address tables for converting logical partial page addresses into physical partial page addresses. The multiplicity of memory blocks of the flash memory are divided into areas which comprise at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for the memory blocks, and a logbook area.

Abstract: Extended commands are transmitted from computer system via a standard interface to a memory system. The computer system accesses logical memory addresses via an application interface using standard read/write commands which are processed by a memory controller in the memory system. A sequence of read commands for at least two logical memory addresses with address values that differ in at least one bit are output by the computer system. The memory controller compares the sequence of different bits with a predefined bit sequence, the magical address sequence. In the event of a match, a subsequent write command for one of the logical memory addresses is used to open a management connection between the computer system and the memory controller, and the useful data contained in the write command are evaluated by the memory controller and are not written to the addressed memory address.

Abstract: A method renews data in a flash memory which is organized in memory units and whose memory units which have been written to are error-protected using ECC words. The memory units which have been written to are test-read in regularly activated test-reading cycles, and either individual memory units which have been written to or all memory units which have been written to are renewed on the basis of the ECC error states which have occurred in a test-reading cycle.

Abstract: A flash memory for a host system has a multiplicity of memory blocks. The memory blocks are subdivided into memory pages which can be written to and each memory page are also subdivided into partial pages and each partial page having a physical partial page address which is assigned a logical partial page address which can be addressed. The physical partial page addresses assigned to the logical partial page addresses are able to be determined using hierarchically organized structures of address tables for converting logical partial page addresses into physical partial page addresses. The multiplicity of memory blocks of the flash memory are divided into areas which comprise at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for the memory blocks, and a logbook area.