Abstract: Some embodiments of the invention include an interconnect structure to transfer data among a plurality of devices. The interconnect structure includes a crossbar and a number of interconnect branches coupled to the crossbar. Each of the interconnect branches includes a number of connector circuits coupled in series to transfer data in a group of devices of the plurality of devices. The crossbar includes a number of connector circuits coupled in series to allow one group of devices from one interconnect branch to exchange data with another group of devices from another interconnect branch. Other embodiments are described and claimed.

Abstract: Some embodiments of the invention include an interconnect structure to transfer data among a plurality of devices. The interconnect structure includes a crossbar and a number of interconnect branches coupled to the crossbar. Each of the interconnect branches includes a number of connector circuits coupled in series to transfer data in a group of devices of the plurality of devices. The crossbar includes a number of connector circuits coupled in series to allow one group of devices from one interconnect branch to exchange data with another group of devices from another interconnect branch. Other embodiments are described and claimed.

Abstract: Some embodiments of the invention include an interconnect structure having a plurality of connector circuits to transfer messages among a number of devices. Each of the connector circuits includes a data transfer unit to transfer messages and a clock unit to provide timing to transfer the messages. The interconnect structure propagates a master clock signal serially through the clock units of the connector circuits to generate a number of different input clock signals. The timing provided by each of the clock units is based on the timing of one of the input clock signals. Other embodiments are described and claimed.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: A programmable integrated circuit (IC) arrangement includes at least one input/output terminal, at least two receiver/source terminals for selectable electrical connection to the at least one input/output terminal, and a plurality of layers electrically interconnected with one another and providing electrical connection between the at least one input/output terminal and at least one of the at least two receiver/source terminals. At least a sub-plurality of the plurality of layers includes electrically conductive components selectably providable at at least two positions so as to selectably program electrical connection between the at least one input/output terminal and the at least two receiver/source terminals. The selectably providable electrically conductive components include ones of selectably providable vias, switch-contacts and well regions. The plurality of layers can include many different types and constructions.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: The invention is directed to a programmable IC (integrated circuit) arrangement. Included are: at least one input/output terminal; at least two receiver/source terminals for selectable electrical connection to the at least one input/output terminal; and a plurality of layers electrically interconnected with one another and providing electrical connection between the at least one input/output terminal and at least one of the at least two receiver/source terminals. At least a sub-plurality of the plurality of layers includes electrically conductive components selectably providable at at least two positions so as to selectably program electrical connection between the at least one input/output terminal and the at least two receiver/source terminals. The selectably providable electrically conductive components include ones of selectably providable vias, switch-contacts and well regions.

Abstract: The invention is directed to a programmable IC (integrated circuit) arrangement. Included are: at least one input/output terminal; at least two receiver/source terminals for selectable electrical connection to the at least one input/output terminal; and a plurality of layers electrically interconnected with one another and providing electrical connection between the at least one input/output terminal and at least one of the at least two receiver/source terminals. At least a sub-plurality of the plurality of layers includes electrically conductive components selectably providable at at least two positions so as to selectably program electrical connection between the at least one input/output terminal and the at least two receiver/source terminals. The selectably providable electrically conductive components include ones of selectably providable vias, switch-contacts and well regions.

Abstract: A sense circuit for programming a fuse device and sensing the fuse device's state is disclosed. The sense circuit utilizes sense transistors that are formed by high voltage VDNMOS transistors. This allows a higher programming voltage to be used in the programming of the fuse device.

Abstract: A sense circuit for programming a fuse device and sensing the fuse device's state is disclosed. The sense circuit utilizes sense transistors that are formed by high voltage VDNMOS transistors. This allows a higher programming voltage to be used in the programming of the fuse device.

Abstract: A high-sensitivity fuse-based storage cell. A first circuit branch including a first fuse is coupled to a second circuit branch including a second fuse in a current mirror configuration. An output node is coupled to the first circuit branch and responsive to a sense enable signal to indicate a logical "1" if the first fuse is programmed and the second fuse is unprogrammed or a logical "0" if the first fuse is unprogrammed and the second fuse is programmed.

Abstract: A static, self-biased, low current sensing circuit for sensing the state of a fuse. A first branch includes a first sensing transistor, a first fuse coupled to a first terminal of the first sensing transistor, and a first load coupled to the opposite terminal of the first sensing transistor. The fuse has an unprogrammed state characterized by a first resistance, and a programmed state in which the fuse has a second resistance. A second reference branch is coupled to the first branch in a current mirror configuration and includes a second sensing transistor, a predetermined reference resistance coupled to a first terminal of the second sensing transistor, and a second load coupled to the opposite terminal of the second sensing transistor. The reference resistance is matched to the fuse device in an un-programmed state. Combinatorial logic coupled to the first and second load devices receives a sense enable signal.

Abstract: A fuse sensing circuit comprises a first branch includes a first sensing transistor, and a fuse coupled to the source of the first sensing transistor. The fuse has a programmed state characterized by a first resistance, and an unprogrammed state in which the fuse has a second resistance. A second reference branch is coupled to the first branch in a current mirror configuration and includes a second sensing transistor, and a predetermined reference resistance coupled to the source of the second sensing transistor. The reference resistance is matched to the fuse device in an un-programmed state. The potential at an output node coupled to the first sensing transistor is determined by the state of the fuse device, such that the potential of the output node is within a first voltage range if the fuse device is programmed, and a second voltage range if the fuse device is un-programmed.

Abstract: A flip-flop circuit is described. The flip-flop circuit receives the data signal from a data input, receives a trigger signal from a trigger input, generates a pulse signal in response to an edge in the trigger signal, and stores the data signal in response to the pulse. Alternatively, the flip-flop circuit receives a data signal through a data input, receives a trigger signal through a trigger input, stores the data signal in a latch, and suppresses the trigger signal to the latch when the data signal stored in the latch corresponds to the data signal received through the data input.

Abstract: Emitter-base protection for a first bipolar transistor formed as part of a BiCMOS circuit. A second bipolar transistor is formed in the same well as the first bipolar transistor with both transistors using the well as their collectors. A current path through the collector-emitter of the second transistor provides current to the base of the first transistor maintaining the emitter-to-base voltage of the first transistor at a relatively low reverse potential.

Abstract: An improved shift register uses fewer than 2*N latches, where N is the capacity in bits of the shift register and also the propagation delay from the input to the output of the shift register in terms of the system clock. An m-phase set of clocks are used, where m is an even number larger than two and and the duration of each clock phase is one half of the period of the system clock. The latches are arranged in m/2 strings of length 2N/(m-1), instead of one long string. The strings of latches are offset with respect to each other by two phases in terms of their connection to the multiphase clock, with each successive latch in each string being enabled by the clock signal whose phase immediatedly precedes the phase of the clock signal used to enable the preceding latch in that string. A multiplexer at the output puts the data from the multiple strings of latches back into one serial output stream.