Abstract: A peripheral device, connected to an address bus, which has yet to be assigned an I/O address has a pin connected to a configuration select output of a control logic circuit (or a CPU). The peripheral device is reset upon start-up of the system and is not yet required to respond to normal bus accesses or traffic. The CPU analyzes the available addresses in the address space and selects an available I/O address for assignment to that peripheral device. In one embodiment, the CPU then sends a serial bit stream containing the selected I/O address to that peripheral device over a configuration select line. In another embodiment, the CPU asserts a configuration select signal to the peripheral device. The CPU then transmits the selected I/O address to the peripheral device on the address bus. The transmitted I/O address is then stored in the peripheral device, and the device will now respond to this I/O address during subsequent operation of the system.

Abstract: Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM.'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft.RTM.'s DOS, IBM.RTM.'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels.

Abstract: A computer system includes a peripheral device connector interface that automatically identifies the type of peripheral device, if any, coupled to the interface and configures itself for handling data flows to and from peripheral devices of the identified type. The system includes a connector that receives a number of peripheral identification signals that are generated by a peripheral device attached to the connector. Peripheral device data signals, which are also received at the connector, are routed by a connector interface. A number of interface circuits are provided to control the different types of peripheral devices that may be attached to the connector. The interface circuits are coupled to configuration registers that provide operational information for the interface circuits. A transition detector identifies any change in the peripheral identification signals. Any change in the peripheral identification signals corresponds to a change in the peripheral device attached to the connector.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: Each of the identical register sets associated with each of the multiple channels of a peripheral device includes an initialization register. Setting the appropriate bit in the initialization register of any one of the channels allows the data processing system serviced by the peripheral device to perform a concurrent write operation to the same selected register in each channel enabled for a concurrent write. The concurrent write operation is based on a standard write instruction and a standard system address.

Abstract: Data characters to be transferred from a peripheral device to a central processing unit are serially shifted into the receiver shift register of a universal asynchronous receiver/transmitter (UART). A multiple byte first-in-first-out memory stores a plurality of data characters received by the shift register. The UART checks the status of each data character stored in the FIFO to determine whether it will trigger an exception, A bytes till exception register indicates the number of data characters remaining in the FIFO until an exception is encountered. Then, upon request by the CPU, the UART provides the count of consecutive valid data characters from the top of the FIFO to the first exception, eliminating the need to check status on every transferred byte. Each of the multiple channels of the UART includes an Initialization Register. Setting the appropriate bit Initialization Register of any UART channel allows concurrent writes to the same selected register in each channel's register set.

Abstract: Data characters to be transferred from a peripheral device to a central processing unit are serially shifted into the receiver shift register of a universal asynchronous receiver/transmitter (UART). A multiple byte first-in-first-out memory stores a plurality of data characters received by the shift register. The UART checks the status of each data character stored in the FIFO to determine whether it will trigger an exception. A bytes till exception register indicates the number of data characters remaining in the FIFO until an exception is encountered. Then, upon request by the CPU, the UART provides the count of consecutive valid data characters from the top of the FIFO to the first exception, eliminating the need to check status on every transferred byte. Each of the multiple channels of the UART includes an Initialization Register. Setting the appropriate bit Initializatioin Register of any UART channel allows concurrent writes to the same selected register in each channel's register set.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead.The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communications station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.