Abstract: A method, system and computer program product for verifying a result of a floating point square root operation is provided. The method includes: receiving a result of a floating point square root operation for an operand; performing a comparison of a magnitude of a least significant bit (LSB) of the operand and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.

Abstract: A method, system and computer program product for verifying a result of a floating point division operation are provided. The method includes: receiving a result of a floating point division operation for a dividend and a divisor; performing a comparison of a magnitude of a least significant bit (LSB) of the dividend and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.

Abstract: A method, computer program product and a system for detecting errors in a result of a fixed-point division operation are provided. The method includes: receiving a result of a fixed-point division operation for a dividend and a divisor; performing a first comparison of the divisor and a remainder of the result; performing a second comparison of a sign of the dividend and a sign of the remainder; and determining whether the result is correct based on the first comparison and the second comparison.

Abstract: A method, computer program product and a system for controlling a fixed point division operation are provided. The method includes: receiving an instruction to perform a division operation for a dividend and a divisor, the operation comprising a maximum number of iterations to produce a quotient having a maximum precision; calculating a magnitude of at least one of the dividend and the divisor; determining a quotient precision based on the magnitude; and computing a required number of iterations needed to produce the quotient precision and performing the number of iterations.

Abstract: Enabling application instructions to access mathematical functions from an accelerated function library to perform instructions. In the performance of the instructions, applying a predefined test instruction on a value, the value being at least one of an input argument, an intermediate result or a final result to determine if the value is a general-case or a predetermined special-case. Responsive to a determination that the value is a special-case, performing a predetermined set of special-case instructions for the performance of the mathematical function.

Abstract: A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

Abstract: A method, computer program product and a system for controlling a fixed point division operation are provided. The method includes: receiving an instruction to perform a division operation for a dividend and a divisor, the operation comprising a maximum number of iterations to produce a quotient having a maximum precision; calculating a magnitude of at least one of the dividend and the divisor; determining a quotient precision based on the magnitude; and computing a required number of iterations needed to produce the quotient precision and performing the number of iterations.

Abstract: A method, system and computer program product for verifying a result of a floating point division operation are provided. The method includes: receiving a result of a floating point division operation for a dividend and a divisor; performing a comparison of a magnitude of a least significant bit (LSB) of the dividend and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.

Abstract: A method, computer program product and a system for detecting errors in a result of a fixed-point division operation are provided. The method includes: receiving a result of a fixed-point division operation for a dividend and a divisor; performing a first comparison of the divisor and a remainder of the result; performing a second comparison of a sign of the dividend and a sign of the remainder; and determining whether the result is correct based on the first comparison and the second comparison.

Abstract: A method, system and computer program product for verifying a result of a floating point square root operation is provided. The method includes: receiving a result of a floating point square root operation for an operand; performing a comparison of a magnitude of a least significant bit (LSB) of the operand and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.

Abstract: A floating point result in a processor is efficiently normalized by predicting the mantissa shift required to normalize the result to an error of one bit position in one direction, resulting in minimum and maximum predicted shifts. Concurrently with an addition of operands to generate a result mantissa, an inversion of the minimum predicted shift is added to the operand exponent to generate an intermediate exponent corresponding to a maximum predicted shift. When the operand addition is complete, the result mantissa is partially shifted in response to the minimum predicted shift. The location of the leading one is then ascertained and compared to the remaining minimum predicted shift. If the minimum predicted shift is the actual shift required to normalize the result, the result mantissa is further shifted by the remaining minimum predicted shift and an exponent carry-in is asserted.

Abstract: A method and system are described, which utilize timing analysis to verify a digital circuit design that includes a plurality of dynamic logic circuit cells employing diverse circuit techniques and that may also include static logic circuit cells. For each dynamic circuit cell, a set of timing constraints is defined based upon the circuit technique employed by the associated dynamic logic circuit cell. Each timing constraint prevents a possible mode of failure of the associated dynamic logic circuit cell. The digital circuit design is then verified. The verification includes a determination of whether or not each dynamic logic circuit cell satisfies its respective set of timing constraints while connected to the other circuit cells. In an embodiment in which the digital circuit design includes a static logic circuit cell, the verification includes a verification that the static logic circuit cell has a correct inversion relationship between its input and output.

Abstract: A device for aligning the radix point of an unaligned binary result of a floating point operation to a normalized or denormalized position is provided. The device comprises an alignment circuit that produces a shift alignment vector indicating the position of the most significant bit of the unaligned result that is set, when a normalized result is required, and that produces a shift alignment vector indicating the position of a bit of the unaligned result having the weight of a minimum allowable exponent for a given format, when a denormalized result is required. A shift register responsive to the alignment circuit shifts the unaligned result by the number of bits indicated by the shift alignment vector.

Abstract: An adder circuit is disclosed having an improved carry lookahead arrangement. The number of carry lookahead stages required is log n, where n is equal to the number of bits in the adder. This arrangement has fanout limit based on the number of sets of propagate and generate signals which can be combined at each bit location of each stage. For example, if two-way merge circuits are used to combine two sets of signals together, then the maximum fanout from the previous stage would be limited to two (2). If four-way merge circuits were used, then the fanout would be limited to four (4). This low fanout is achieved without increasing the number of stages by overlapping the groups that are combined in each step.

Abstract: An evaluation tree circuit is disclosed that produces a generate, a propagate, and a zero output for use in carry lookahead adders. Another evaluation tree circuit is disclosed that merges the generate, propagate, and zero signals from several adjacent bits or groups of bits. These evaluation trees may be used in self-resetting CMOS or CVSL circuits. They can be used to reduce the number of levels of logic in a carry lookahead adder. They can also be used to form a magnitude comparator, which is also disclosed.

Abstract: An improved test circuit and method for integrated circuits are disclosed. The test circuit uses a level sensitive scan design for use with a multiplexor having a plurality of pass gates. The test circuit includes a plurality of latches, each having a functional input, a scan input and an output. The outputs are coupled to the multiplexor pass gates. A first set of mutually exclusive, or orthogonal, signals is placed on the functional inputs of the latches for selecting one of the pass gates. A signal encoder is used to form a reduced set of signals, based on the first set of signals. The reduced set of signals is further modified by a modifying means, such as a shift register. The modified signal is then decoded by a decoding means for generating the next set of orthogonal signals placed on the scan inputs. Also, an output signal is then transmitted as an evaluation signal to confirm the accuracy of the integrated circuit.

Abstract: An apparatus and method for anticipating leading zeros/ones used in normalizing the results of a full adder. The propagate (P), generate (G) and zero (Z) states of the two inputs to the adder are combined in two stages of logic to derive a pair of state outputs L.phi.S and L1S which fully specify by respective bit strings the leading zero and leading one conditions of the output from the adder. The two state bit strings, one representing the leading zero evaluation and the second representing the leading one evaluation, are then compared to determine which one of the two is applicable, correspondingly indicating whether the adder result is a positive or a negative value, and the number of leading bit positions requiring shifted removal during the normalization process. The leading 0/1 anticipator according to the present invention lends itself to high speed and low device count circuit implementations.

Abstract: A mask generation circuit for generating a bit mask sequence of 2.sup.N bits including a first logic circuit having a single level of combinational logic for receiving an N bit indication of the bit mask sequence and for providing an output of 2.sup.q plus 2.sup.P signals to a second logic circuit that includes 2.sup.P identical logical units of not more than 2 levels of combinational logic each connected in parallel and each unit including 2.sup.q -1 repeating circuit sets. These units are connected to receive the signals from the first logic circuit and provide therefrom the ibt mask sequence. In one embodiment of the present invention, a bit mask generator is provided that includes a first edge generator circuit and a second edge generator circuit where each of the edge generator circuits are provided N bit indications indicating the binary digital sequence transition point.

Abstract: A data processing circuit that performs either a merge or Boolean logic operation on data within a single clock cycle in response to an instruction. The circuit includes a control circuit for receiving an instruction during a clock cycle and providing a plurality of control signals in response to the instruction. Data selector circuitry is included for providing a plurality of data words in response to the control signals from the control circuit. Additionally, a rotator is connected to at least one data selector for rotating at least one of the data words in response to a control signal from the control circuit. Logic circuitry is provided for logically combining bits form the rotator and the data selector circuitry in response to control signals from the control circuit for providing data output within the single clock cycle.

Abstract: A programmable logic array having a plurality of electrically isolated input lines connected to an input circuit for providing an input signal to one of the plurality of input lines. Also included are a plurality of electrically isolated output lines positioned relative to the input lines to form an array having a plurality of non-conductive intersections. A plurality of programmable circuits, each positioned at a selected one of the intersections and interconnecting an adjacent input line, an adjacent output line and one of two output potentials that define one of two output states are provided. The programmable circuit is further connected to the input line such that when an input signal is received on the input line, the selected output potential representing one of the two output states is provided on the output line.