Patents by Inventor Martin Schatz
Martin Schatz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230306291Abstract: A system for generating simulated data is disclosed. The system may determine items of content utilized by a network. The system may also retrieve one or more data patterns associated with one or more features associated with the content. The system may also determine a plurality of indices associated with the data patterns. The system may also generate, based on the data patterns and the plurality of indices, simulated data associated with the content.Type: ApplicationFiled: March 22, 2022Publication date: September 28, 2023Inventors: Martin SCHATZ, Dmitry Vengertsev, Yifan Liu, Ilana Marisa Arbisser, Yuchen Hao, Muhammet Mustafa Ozdal
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Patent number: 11699081Abstract: The disclosed computer-implemented method may include (1) receiving, at a hardware accelerator that supports an ANN, an activation data set that is to undergo a convolution operation via a filter kernel of the ANN, (2) receiving, at the hardware accelerator, an argument indicating that the filter kernel exceeds at least one boundary of the activation data set when slid across a certain position during the convolution operation, (3) determining, based at least in part on the argument, that the hardware accelerator is to generate padding data at the boundary of the activation data set in connection with the certain position of the filter kernel, and then (4) performing, at the hardware accelerator, the convolution operation by processing a portion of the activation data set and the padding data when the filter kernel slides across the certain position. Various other systems and methods are also disclosed.Type: GrantFiled: December 20, 2019Date of Patent: July 11, 2023Assignee: Meta Platforms, Inc.Inventors: Ehsan Khish Ardestani Zadeh, Martin Schatz, Krishnakumar Narayanan Nair, Yuchen Hao, Abdulkadir Utku Diril, Rakesh Komuravelli
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Patent number: 11631026Abstract: Systems, methods, and non-transitory computer readable media are configured to train a machine learning model. The training can be based on a training set of embeddings of a first type and a training set of embeddings of a second type. The machine learning model can be trained to receive an embedding of a second type and to output a corresponding embedding of the first type. A given embedding of the second type can be provided as input to the machine learning model. An embedding of the first type can be obtained from the machine learning model. The embedding of the first type can correspond to the given embedding of the second type.Type: GrantFiled: July 13, 2017Date of Patent: April 18, 2023Assignee: Meta Platforms, Inc.Inventors: Martin Schatz, Bradley Ray Green
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Patent number: 11599181Abstract: A computer-implemented method may include (1) maintaining (a) a filter matrix in a filter cache included in a local memory device (LMD) included in a hardware accelerator, and (b) a plurality of activation matrices corresponding to different rows of an activation volume in an activation cache included in the LMD, (2) for each activation matrix, directing a matrix multiplication unit (MMU) included in the hardware accelerator to execute a matrix multiplication operation (MMU) using the filter matrix and the activation matrix, (3) loading an additional filter matrix into the filter cache, and (4) directing the MMU to execute a plurality of additional MMOs, each additional MMO using one filter matrix included in the filter cache and one activation matrix included in the activation cache, such that the MMU reuses the filter matrix for at least one additional MMO and uses the additional filter matrix for a different additional MMO.Type: GrantFiled: December 23, 2019Date of Patent: March 7, 2023Assignee: Meta Platforms, Inc.Inventors: Krishnakumar Narayanan Nair, Abdulkadir Utku Diril, Yuchen Hao, Thomas Mark Ulrich, Rakesh Komuravelli, Ehsan Khish Ardestani Zadeh, Martin Schatz
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Patent number: 11580192Abstract: A processor system comprises a plurality of processing elements. Each processing element includes a corresponding convolution processor unit configured to perform a portion of a groupwise convolution. The corresponding convolution processor unit determines multiplication results by multiplying each data element of a portion of data elements in a convolution data matrix with a corresponding data element in a corresponding groupwise convolution weight matrix. The portion of data elements in the convolution data matrix that are multiplied belong to different channels and different groups. For each specific channel of the different channels, the corresponding convolution processor unit sums together at least some of the multiplication results belonging to the same specific channel to determine a corresponding channel convolution result data element.Type: GrantFiled: April 8, 2020Date of Patent: February 14, 2023Assignee: Meta Platforms, Inc.Inventors: Rakesh Komuravelli, Krishnakumar Narayanan Nair, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
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Patent number: 11537865Abstract: A processor system comprises a first and second group of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate convolution weight matrix for each channel. Each register stores at least one data element from each convolution weight matrix. The hardware channel convolution processor unit is configured to multiply each data element in the first group of registers with a corresponding data element in the second group of registers and sum together the multiplication results for each specific channel to determine corresponding channel convolution result data elements in a corresponding channel convolution result matrix.Type: GrantFiled: February 18, 2020Date of Patent: December 27, 2022Assignee: Meta Platforms, Inc.Inventors: Krishnakumar Narayanan Nair, Rakesh Komuravelli, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
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Patent number: 11520853Abstract: A processor system comprises two groups of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate matrix for each channel. Each register stores at least one data element from each matrix. The hardware channel convolution processor unit is configured to multiply each data element in a first and second portion of the first group of registers with a corresponding data element in the second group of registers to determine corresponding multiplication results and sum together the multiplication results for each specific channel to determine two corresponding channel convolution result data elements in a corresponding channel convolution result matrix.Type: GrantFiled: February 28, 2020Date of Patent: December 6, 2022Assignee: Meta Platforms, Inc.Inventors: Krishnakumar Narayanan Nair, Rakesh Komuravelli, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
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Patent number: 11501147Abstract: A disclosed computer-implemented method may include maintaining, within a local memory device (LMD) included in a hardware accelerator (1) a filter matrix corresponding to a filter location included in each of a set of filters of a convolutional layer of an artificial neural network (ANN), and (2) a set of activation vectors corresponding to an active region of an activation volume input into the convolutional layer. The method may also include determining that the active region of the activation volume is contiguous with a padding region associated with at least a portion of the activation volume. The method may further include directing a matrix multiplication unit (MMU) included in the hardware accelerator to execute a matrix multiplication operation (MMO) using the filter matrix and an activation matrix that may include (1) the set of activation vectors, and (2) at least one padding vector corresponding to the padding region.Type: GrantFiled: January 30, 2020Date of Patent: November 15, 2022Assignee: Meta Platforms, Inc.Inventors: Krishnakumar Narayanan Nair, Ehsan Khish Ardestani, Martin Schatz, Yuchen Hao, Abdulkadir Utku Diril, Rakesh Komuravelli
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Patent number: 11443013Abstract: A processor system comprises a hardware channel convolution processor unit and dot product processor unit. The channel convolution processor unit is configured to perform depthwise convolution, including by multiplying each data element of a first group of data elements of a convolution data matrix with a corresponding data element of a second group of data elements of a plurality of depthwise convolution weight matrices and summing together, for each specific channel, multiplication results corresponding to the specific channel to determine one corresponding result data element in a corresponding channel convolution result matrix to calculate a portion of depthwise convolution results.Type: GrantFiled: March 23, 2020Date of Patent: September 13, 2022Assignee: Meta Platforms, Inc.Inventors: Rakesh Komuravelli, Krishnakumar Narayanan Nair, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
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Publication number: 20210334072Abstract: A processor system comprises a plurality of dot product processor units and element-wise multiplication units. The dot product processor units perform a depthwise convolution of a data matrix with a separate depthwise convolution weight matrix for each data matrix channel. Each dot product processor unit performs at least a portion of the depthwise convolution for one or more data matrix channels. The element-wise multiplication units perform multiplication operations of a pointwise convolution. Each element-wise multiplication unit applies to each depthwise convolution partial result element received from one or more of the dot product processor units a corresponding data element from each of a plurality of pointwise convolution weight filters to determine element-wise multiplication unit results. The processor system sums together different groups of data elements from the element-wise multiplication unit results to at least in part calculate different data elements of a result of the pointwise convolution.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: Rakesh Komuravelli, Krishnakumar Narayanan Nair, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
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Publication number: 20210319076Abstract: A processor system comprises a plurality of processing elements. Each processing element includes a corresponding convolution processor unit configured to perform a portion of a groupwise convolution. The corresponding convolution processor unit determines multiplication results by multiplying each data element of a portion of data elements in a convolution data matrix with a corresponding data element in a corresponding groupwise convolution weight matrix. The portion of data elements in the convolution data matrix that are multiplied belong to different channels and different groups. For each specific channel of the different channels, the corresponding convolution processor unit sums together at least some of the multiplication results belonging to the same specific channel to determine a corresponding channel convolution result data element.Type: ApplicationFiled: April 8, 2020Publication date: October 14, 2021Inventors: Rakesh Komuravelli, Krishnakumar Narayanan Nair, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
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Publication number: 20210294875Abstract: A processor system comprises a hardware channel convolution processor unit and dot product processor unit. The channel convolution processor unit is configured to perform depthwise convolution, including by multiplying each data element of a first group of data elements of a convolution data matrix with a corresponding data element of a second group of data elements of a plurality of depthwise convolution weight matrices and summing together, for each specific channel, multiplication results corresponding to the specific channel to determine one corresponding result data element in a corresponding channel convolution result matrix to calculate a portion of depthwise convolution results.Type: ApplicationFiled: March 23, 2020Publication date: September 23, 2021Inventors: Rakesh Komuravelli, Krishnakumar Narayanan Nair, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
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Publication number: 20210271451Abstract: A processor system comprises two groups of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate matrix for each channel. Each register stores at least one data element from each matrix. The hardware channel convolution processor unit is configured to multiply each data element in a first and second portion of the first group of registers with a corresponding data element in the second group of registers to determine corresponding multiplication results and sum together the multiplication results for each specific channel to determine two corresponding channel convolution result data elements in a corresponding channel convolution result matrix.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Inventors: Krishnakumar Narayanan Nair, Rakesh Komuravelli, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
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Publication number: 20210256363Abstract: A processor system comprises a first and second group of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate convolution weight matrix for each channel. Each register stores at least one data element from each convolution weight matrix. The hardware channel convolution processor unit is configured to multiply each data element in the first group of registers with a corresponding data element in the second group of registers and sum together the multiplication results for each specific channel to determine corresponding channel convolution result data elements in a corresponding channel convolution result matrix.Type: ApplicationFiled: February 18, 2020Publication date: August 19, 2021Inventors: Krishnakumar Narayanan Nair, Rakesh Komuravelli, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
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Publication number: 20210192359Abstract: The disclosed computer-implemented method may include (1) receiving, at a hardware accelerator that supports an ANN, an activation data set that is to undergo a convolution operation via a filter kernel of the ANN, (2) receiving, at the hardware accelerator, an argument indicating that the filter kernel exceeds at least one boundary of the activation data set when slid across a certain position during the convolution operation, (3) determining, based at least in part on the argument, that the hardware accelerator is to generate padding data at the boundary of the activation data set in connection with the certain position of the filter kernel, and then (4) performing, at the hardware accelerator, the convolution operation by processing a portion of the activation data set and the padding data when the filter kernel slides across the certain position. Various other systems and methods are also disclosed.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: Ehsan Khish Ardestani Zadeh, Martin Schatz, Krishnakumar Narayanan Nair, Yuchen Hao, Abdulkadir Utku Diril, Rakesh Komuravelli
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Patent number: 11010202Abstract: A specification of an operation to perform one or more element-wise sums of specified portions of a matrix is received. The specification of the operation is analyzed to select a type of processing load partitioning to be applied. Based on the selected type of processing load partitioning to be applied, processing required to perform the operation is partitioned across a plurality of physical processing elements in parallel. The partitioned processing is distributed to the physical hardware processing elements to perform in parallel the element-wise sums of the specified portions of the matrix.Type: GrantFiled: August 6, 2019Date of Patent: May 18, 2021Assignee: Facebook, Inc.Inventors: Martin Schatz, Amin Firoozshahian
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Publication number: 20210042116Abstract: A specification of an operation to perform one or more element-wise sums of specified portions of a matrix is received. The specification of the operation is analyzed to select a type of processing load partitioning to be applied. Based on the selected type of processing load partitioning to be applied, processing required to perform the operation is partitioned across a plurality of physical processing elements in parallel. The partitioned processing is distributed to the physical hardware processing elements to perform in parallel the element-wise sums of the specified portions of the matrix.Type: ApplicationFiled: August 6, 2019Publication date: February 11, 2021Inventors: Martin Schatz, Amin Firoozshahian
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Publication number: 20190034973Abstract: Systems, methods, and non-transitory computer-readable media can identify a target page and an advertising campaign comprising one or more advertisements associated with the target page. One or more users are identified for inclusion in a base audience based on page information associated with the target page. One or more users are identified for inclusion in an expanded audience based on expanded audience criteria. The advertising campaign is presented to a smart audience comprising the base audience and the expanded audience.Type: ApplicationFiled: July 26, 2017Publication date: January 31, 2019Inventors: Jinyi Yao, Martin Schatz, Arash Ashari, Vijay Rangarajan, Liushan Yang, Iris Yui Chang
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Publication number: 20190019105Abstract: Systems, methods, and non-transitory computer readable media are configured to train a machine learning model. The training can be based on a training set of embeddings of a first type and a training set of embeddings of a second type. The machine learning model can be trained to receive an embedding of a second type and to output a corresponding embedding of the first type. A given embedding of the second type can be provided as input to the machine learning model. An embedding of the first type can be obtained from the machine learning model. The embedding of the first type can correspond to the given embedding of the second type.Type: ApplicationFiled: July 13, 2017Publication date: January 17, 2019Inventors: Martin Schatz, Bradley Ray Green
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Patent number: 6725194Abstract: In a speech recognition device (1) comprising receiving means (36) for receiving voice information (AI) uttered by a speaker and including speech coefficient memory means (38) for storing a speech coefficient indicator (SKI, PRI, SMI, WI) and including speech recognition means (42) which are arranged for recognizing text information (RTI) corresponding to the received voice information (AI) by evaluating the voice information (AI) and the speech coefficient indicator (SKI, PRI, SMI, WI), and including correction means (49) for correcting the recognized text information (RTI) and for producing corrected text information (CTI), text comparing means (52) are provided for comparing the recognized text information (RTI) with the corrected text information (CTI) and for determining at least a correspondence indicator (CI) and the adjusting means (50) are provided for adjusting the stored speech coefficient indicator (SKI, PRI, SMI, WI) by evaluating only one of such text parts (P2) of the corrected text informationType: GrantFiled: July 6, 2000Date of Patent: April 20, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Heinrich Bartosik, Walter Müller, Martin Schatz