Abstract: Methods and apparatus are provided for imaging a response of a sample to radiative heating. A method in accordance with one embodiment has steps of: illuminating a first area of the sample with a radiative heating beam; illuminating a portion of the first area with a probe beam; collecting light exiting the sample due to interaction of the probe beam with the sample; superimposing the light exiting the sample with a reference beam derived from the probe beam, wherein the reference is characterized by an optical phase relative to the probe beam; detecting a spatial portion of the light exiting the sample and the reference beam with at least one detector to generate an interference signal; and processing the interference signal to obtain an image of the sample associated with absorption of the radiative heating beam.

Abstract: Methods and apparatus are provided for imaging a response of a sample to radiative heating. A method in accordance with one embodiment has steps of: illuminating a first area of the sample with a radiative heating beam; illuminating a portion of the first area with a probe beam; collecting light exiting the sample due to interaction of the probe beam with the sample; superimposing the light exiting the sample with a reference beam derived from the probe beam, wherein the reference is characterized by an optical phase relative to the probe beam; detecting a spatial portion of the light exiting the sample and the reference beam with at least one detector to generate an interference signal; and processing the interference signal to obtain an image of the sample associated with absorption of the radiative heating beam.

Abstract: A cylinder (10) comprising a cylindrical body (11) is provided. A first proportion of the circumferential face (48) of the cylindrical body (11) is of porous and gas-permeable configuration and a second proportion of the circumferential face (48) of the cylindrical body (11) is of gas-impermeable configuration, wherein the porous, gas-permeable first proportion of the circumferential face (48) is in communication with at least one gas supply line and wherein the first proportion of the circumferential face (48) amounts to at least 0.1% and at most 50%. Further, a corresponding adapter sleeve and a corresponding printing forme cylinder are provided.

Abstract: The invention relates to a device for conducting near-field optical measurements of a sample comprising a wavelength-tunable monochromatic light source. Further the invention relates to methods for measuring the near-field using such a device.

Abstract: The invention relates to a cylinder (10) comprising a cylindrical body (11). In the case of this cylinder a first proportion of the circumferential face (48) of the cylindrical body (11) is of porous and gas-permeable configuration and a second proportion of the circumferential face (48) of the cylindrical body (11) is of gas-impermeable configuration, where the porous, gas-permeable first proportion of the circumferential face (48) is in communication with at least one gas supply line and where the first proportion of the circumferential face (48) amounts to at least 0.1% and at most 50%. Further aspects of the invention relate to a corresponding adapter sleeve (10) and to a corresponding printing forme cylinder.

Abstract: The invention relates to a device for conducting near-field optical measurements of a sample comprising a wavelength-tunable monochromatic light source. Further the invention relates to methods for measuring the near-field using such a device.

Abstract: In a measuring apparatus (8) having a measuring unit (1) according to the invention a spatially resolved measurement result detected using the measuring unit (1) of an object (16) is converted into a false-color image, and the false-color image is cast back or projected onto the object (16) by a display device (3).

Abstract: Methods and apparatus for imaging a phase or amplitude that characterizes a scattered field emanating from a physical medium. A local probe is stepped to a plurality of successive probe positions and illuminated with an illuminating beam, while a specified phase function is imposed on a reference beam relative to the illuminating beam. A field associated with the scattered field is superimposed with the reference beam and the detection of both yields a detected signal which is recorded as a function of probe position in order to obtain a hologram. The holograph is transformed, filtered, and retransformed to generate an image. Alternatively, the illuminating beam may directly illuminate successive positions of the physical medium.

Abstract: Methods and apparatus for imaging a phase or amplitude that characterizes a scattered field emanating from a physical medium. A local probe is stepped to a plurality of successive probe positions and illuminated with an illuminating beam, while a specified phase function is imposed on a reference beam relative to the illuminating beam. A field associated with the scattered field is superimposed with the reference beam and the detection of both yields a detected signal which is recorded as a function of probe position in order to obtain a hologram. The holograph is transformed, filtered, and retransformed to generate an image. Alternatively, the illuminating beam may directly illuminate successive positions of the physical medium.

Abstract: In a measuring apparatus (8) having a measuring unit (1) according to the invention a spatially resolved measurement result detected using the measuring unit (1) of an object (16) is converted into a false-color image, and the false-color image is cast back or projected onto the object (16) by a display device (3).

Abstract: A memory device in a semiconductor substrate includes at least one temperature sensor to provide a temperature dependent signal and at least one circuit to dissipate heat in response to a control signal. A control circuit is coupled to the at least one circuit and is operable to generate the control signal in response to the temperature dependent signal.

Abstract: The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.

Abstract: Test method and production method for testing a semiconductor circuit comprising a plurality of subcircuits. The semiconductor circuit is produced according to specification stipulations comprising a design based on a hardware description language for a functional implementation, a logic synthesis for a structural implementation, a layout design for a topological implementation and processing a semiconductor substrates in accordance with the layout design. A test pattern having test signal sequences is coupled into the semiconductor circuit and functional results are coupled out. Test signal lengths and/or test signal levels are selected from a previously generated test parameter list, wherein the test parameter list is generated during the logic synthesis.

Abstract: The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock.

Abstract: A memory device in a semiconductor substrate includes at least one temperature sensor to provide a temperature dependent signal and at least one circuit to dissipate heat in response to a control signal. A control circuit is coupled to the at least one circuit and is operable to generate the control signal in response to the temperature dependent signal.

Abstract: The invention provides a method for testing circuit units to be tested in a test apparatus, different identification units being assigned to the circuit units to be tested, the circuit units to be tested being connected to the test apparatus, a tester data stream including command blocks being output from the test apparatus, the tester data stream being compared with the identification units, the circuit unit to be tested, the identification unit of which matches the tester data stream output by the test apparatus, being activated and at least one command block for this circuit unit to be tested being processed in the circuit unit to be tested, whereupon the circuit unit to be tested is deactivated.

Abstract: An insertable calibration device for a programmable tester apparatus comprises at least one calibration unit and a control unit. The progammable tester apparatus is configured to test at least one electronic device with electronic circuits. The progammable tester apparatus comprises a holding device, contact-making devices for the electronic device, and tester channels for coupling in signals to the electronic device. The calibration unit is connected to a first tester channel to be calibrated. The calibration unit is configured to detect a calibration signal edge of a calibration signal that is transmitted by the tester apparatus at a certain transmission instant, to detect a reference signal edge of a reference signal that is transmitted by the tester apparatus via a second tester channel at a reference instant, to compare the instants at which the two signal edges arrive, and to output a comparison result.

Abstract: A tester for semiconductor components with a plurality of channels is connected to a specific semiconductor component in order to characterize the signal path between tester and semiconductor component under production conditions. The specific semiconductor component includes measuring units that are connected to connection contacts and in each case provide the functionality of a signal generator, a signal detector, a digital communication interface and a receiving unit for trigger signals. The specific semiconductor component further includes a trigger logic to convey trigger signals between the receiving unit of a first one and the signal generator or detector of a second one of the measuring units.

Abstract: An integrated circuit arrangement comprises at least one one-time programmable storage element, which can be electrically deactivated, having at least one electrically conductive or semi-conductive nanotube or at least one electrically conductive or semi-conductive nanowire.

Abstract: A backwards-compatible memory module is disclosed. According to one aspect, a memory module comprises addressable memory cells organized in organization units having a predetermined number of memory cells, a read/write control device clocked by a first clock signal, a plurality of prefetch registers for initially storing data read from the memory cells wherein the register size corresponds to the predetermined number. In a first operating mode, a switching device clocked by a second clock signal successively couples the prefetch registers to data input/output terminals. The number of data input/output terminals corresponds to the predetermined number. In a second operating mode, the switching device is controlled by at least one address signal and couples at least one of the prefetch registers to the data input/output terminals.