Abstract: A method of determining a timing relationship between modules on a chip, each module being timed by an initiator. The timing relationship being determined on the basis of the power consumptions over time of the initiators and may be determined on the basis of e.g. a sum of the power consumptions or more complex calculations also incorporating the signal path or power delivery network, whereby a voltage drop or current drawn at a position in the chip may be determined. In addition, a parameter, which may be the sum or voltage drop, current or e.g. an energy content within a frequency range, may be determined. This parameter may be varied by e.g. providing different timing relations of initiators, in order to minimize the parameter or adapt it to a requirement as a maximum peak value, maximum difference between max and min peaks, a flatness criteria or the like.