Abstract: A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

Abstract: Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

Abstract: The semiconductor memory device comprises a plurality of memory cells. Each memory cell comprises a respective transistor and a respective capacitor unit. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, the drain area and source area are embedded in the transistor body on a first surface of the transistor body, and a gate structure having a gate dielectric layer and a gate electrode, the gate structure is arranged between the drain area and the source area. An isolation trench is arranged adjacent to said transistor body, having a dielectric layer and a conductive material, wherein the isolation trench is at least partially filled with the conductive material. The conductive material is isolated by said dielectric layer from the transistor body. The capacitor unit is formed by the transistor body representing a first electrode and the conductive material representing the second electrode.

Abstract: A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

Abstract: A floating gate field-effect transistor (400), which is preferably used as a memory cell, has, above or below a floating gate region (407), an electrically insulating layer sequence (408) having a lower layer (409) having a first relative permittivity, having a middle layer (410) having a second relative permittivity, and having an upper layer (411) having a third relative permittivity, the second relative permittivity being greater than the first relative permittivity and greater than the third relative permittivity.

Abstract: Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

Abstract: A floating gate field-effect transistor (400), which is preferably used as a memory cell, has, above or below a floating gate region (407), an electrically insulating layer sequence (408) having a lower layer (409) having a first relative permittivity, having a middle layer (410) having a second relative permittivity, and having an upper layer (411) having a third relative permittivity, the second relative permittivity being greater than the first relative permittivity and greater than the third relative permittivity.