Patents by Inventor Martin Staebler
Martin Staebler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12009769Abstract: A motor system with an input for coupling to a motor control signal that, when presented in a predetermined state, indicates a motor receiving power should be disabled from rotating. The system also includes controller circuitry for providing a disabling signal to motor rotation, independent of processor software control signaling and the power, in response to the control signal.Type: GrantFiled: November 14, 2022Date of Patent: June 11, 2024Assignee: Texas Instruments IncorporatedInventors: Navaneeth Kumar Narayanasamy, Martin Staebler
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Publication number: 20230412431Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.Type: ApplicationFiled: September 1, 2023Publication date: December 21, 2023Inventors: Sadia Arefin KHAN, Anant Shankar KAMATH, Martin STAEBLER, Vikas Kumar THAWANI
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Patent number: 11792051Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.Type: GrantFiled: June 21, 2021Date of Patent: October 17, 2023Assignee: Texas Instruments IncorporatedInventors: Sadia Arefin Khan, Anant Shankar Kamath, Martin Staebler, Vikas Kumar Thawani
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Patent number: 11704276Abstract: A method includes receiving a chip select signal at an SPI client device. The method also includes, responsive to receiving the chip select signal, transmitting a first bit of an SPI transmission to an SPI host device, where the first bit of the SPI transmission is transmitted with a delay based at least in part on a loop propagation delay of an SPI channel. The method includes receiving a clock signal at the SPI client device. The method also includes, responsive to receiving the clock signal, transmitting a second bit of the SPI transmission to the SPI host device.Type: GrantFiled: May 19, 2022Date of Patent: July 18, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kristen N. Mogensen, Matthieu Chevrier, Martin Staebler
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Publication number: 20230072415Abstract: A motor system with an input for coupling to a motor control signal that, when presented in a predetermined state, indicates a motor receiving power should be disabled from rotating. The system also includes controller circuitry for providing a disabling signal to motor rotation, independent of processor software control signaling and the power, in response to the control signal.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Inventors: Navaneeth Kumar Narayanasamy, Martin Staebler
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Patent number: 11579022Abstract: In described examples, a measurement circuit includes an isolated power supply that generates an output signal in response to an input signal. A signal processing circuit is coupled to the isolated power supply and generates a first signal in response to a sense signal. A load manipulator circuit is coupled to the signal processing circuit and the isolated power supply. The load manipulator circuit receives the first signal. A detect circuit is coupled to the isolated power supply and generates a second signal in response to the input signal.Type: GrantFiled: September 9, 2020Date of Patent: February 14, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Navaneeth Kumar Narayanasamy, Martin Staebler
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Patent number: 11502629Abstract: A motor system with an input for coupling to a motor control signal that, when presented in a predetermined state, indicates a motor receiving power should be disabled from rotating. The system also includes controller circuitry for providing a disabling signal to motor rotation, independent of processor software control signaling and the power, in response to the control signal.Type: GrantFiled: December 30, 2020Date of Patent: November 15, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Navaneeth Kumar Narayanasamy, Martin Staebler
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Publication number: 20220292048Abstract: A method includes receiving a chip select signal at an SPI client device. The method also includes, responsive to receiving the chip select signal, transmitting a first bit of an SPI transmission to an SPI host device, where the first bit of the SPI transmission is transmitted with a delay based at least in part on a loop propagation delay of an SPI channel. The method includes receiving a clock signal at the SPI client device. The method also includes, responsive to receiving the clock signal, transmitting a second bit of the SPI transmission to the SPI host device.Type: ApplicationFiled: May 19, 2022Publication date: September 15, 2022Inventors: Kristen N. Mogensen, Matthieu Chevrier, Martin Staebler
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Publication number: 20220209695Abstract: A motor system with an input for coupling to a motor control signal that, when presented in a predetermined state, indicates a motor receiving power should be disabled from rotating. The system also includes controller circuitry for providing a disabling signal to motor rotation, independent of processor software control signaling and the power, in response to the control signal.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Inventors: Navaneeth Kumar Narayanasamy, Martin Staebler
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Patent number: 11341081Abstract: A method includes receiving a chip select signal at an SPI client device. The method also includes, responsive to receiving the chip select signal, transmitting a first bit of an SPI transmission to an SPI host device, where the first bit of the SPI transmission is transmitted with a delay based at least in part on a loop propagation delay of an SPI channel. The method includes receiving a clock signal at the SPI client device. The method also includes, responsive to receiving the clock signal, transmitting a second bit of the SPI transmission to the SPI host device.Type: GrantFiled: March 10, 2021Date of Patent: May 24, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kristen N. Mogensen, Matthieu Chevrier, Martin Staebler
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Patent number: 11290099Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.Type: GrantFiled: October 9, 2020Date of Patent: March 29, 2022Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, Martin Staebler, William Cronin Wallace
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Publication number: 20220074794Abstract: In described examples, a measurement circuit includes an isolated power supply that generates an output signal in response to an input signal. A signal processing circuit is coupled to the isolated power supply and generates a first signal in response to a sense signal. A load manipulator circuit is coupled to the signal processing circuit and the isolated power supply. The load manipulator circuit receives the first signal. A detect circuit is coupled to the isolated power supply and generates a second signal in response to the input signal.Type: ApplicationFiled: September 9, 2020Publication date: March 10, 2022Inventors: Navaneeth Kumar Narayanasamy, Martin Staebler
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Publication number: 20220021562Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.Type: ApplicationFiled: June 21, 2021Publication date: January 20, 2022Inventors: Sadia Arefin KHAN, Anant Shankar KAMATH, Martin STAEBLER, Vikas Kumar THAWANI
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Publication number: 20210028777Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.Type: ApplicationFiled: October 9, 2020Publication date: January 28, 2021Inventors: Thomas Anton LEYRER, Martin STAEBLER, William Cronin WALLACE
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Patent number: 10812060Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.Type: GrantFiled: May 29, 2019Date of Patent: October 20, 2020Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, Martin Staebler, William Cronin Wallace
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Patent number: 10734927Abstract: A sort buffer includes a phase sector determination circuit, a phase sector update circuit, and a phase sector completion circuit. The phase sector determination circuit is configured to determine a phase sector corresponding to a phase of a first sine and cosine sample pair received from an encoder or resolver. The phase sector update circuit is configured to determine whether a second sine and cosine sample pair corresponding to the phase sector is stored in a lookup table (LUT) and, in response to a determination that a second sine and cosine sample pair corresponding to the phase sector is not stored in the LUT, store the first sine and cosine sample pair in the LUT. The phase sector completion circuit is configured to determine whether the LUT has stored, for each of a plurality of phase sectors, a corresponding sine and cosine sample pair.Type: GrantFiled: August 19, 2019Date of Patent: August 4, 2020Assignee: Texas Instruments IncorporatedInventors: Martin Staebler, Ferdinand von Molo
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Patent number: 10547268Abstract: A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.Type: GrantFiled: December 29, 2017Date of Patent: January 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tobias Bernhard Fritz, Martin Staebler, Baher Haroun, Peter Fundaro, Jiri Panacek, Ralf Peter Brederlow
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Publication number: 20190372566Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.Type: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Thomas Anton LEYRER, Martin STAEBLER, William Cronin WALLACE
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Publication number: 20190372488Abstract: A sort buffer includes a phase sector determination circuit, a phase sector update circuit, and a phase sector completion circuit. The phase sector determination circuit is configured to determine a phase sector corresponding to a phase of a first sine and cosine sample pair received from an encoder or resolver. The phase sector update circuit is configured to determine whether a second sine and cosine sample pair corresponding to the phase sector is stored in a lookup table (LUT) and, in response to a determination that a second sine and cosine sample pair corresponding to the phase sector is not stored in the LUT, store the first sine and cosine sample pair in the LUT. The phase sector completion circuit is configured to determine whether the LUT has stored, for each of a plurality of phase sectors, a corresponding sine and cosine sample pair.Type: ApplicationFiled: August 19, 2019Publication date: December 5, 2019Inventors: Martin STAEBLER, Ferdinand von MOLO
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Patent number: 10389281Abstract: A sort buffer includes a phase sector determination circuit, a phase sector update circuit, and a phase sector completion circuit. The phase sector determination circuit is configured to determine a phase sector corresponding to a phase of a first sine and cosine sample pair received from an encoder or resolver. The phase sector update circuit is configured to determine whether a second sine and cosine sample pair corresponding to the phase sector is stored in a lookup table (LUT) and, in response to a determination that a second sine and cosine sample pair corresponding to the phase sector is not stored in the LUT, store the first sine and cosine sample pair in the LUT. The phase sector completion circuit is configured to determine whether the LUT has stored, for each of a plurality of phase sectors, a corresponding sine and cosine sample pair.Type: GrantFiled: October 20, 2016Date of Patent: August 20, 2019Assignee: Texas Instruments IncorporatedInventors: Martin Staebler, Ferdinand von Molo