Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.

Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.

Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.

Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.

Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.

Abstract: A method for manufacturing a memory cell in accordance with various embodiments may include: forming at least one charge storing memory cell structure over a substrate, the charge storing memory cell structure having a first sidewall and a second sidewall opposite the first sidewall; forming an electrically conductive layer over the substrate and the charge storing memory cell structure; patterning the electrically conductive layer to form a spacer at the first sidewall and a blocking structure at the second sidewall of the charge storing memory cell structure; implanting first dopant atoms to form a first doped region in the substrate proximate the spacer, wherein the first dopant atoms are blocked by the blocking structure; removing the blocking structure after implanting the first dopant atoms; implanting second dopant atoms to form a second doped region in the substrate proximate the second sidewall of the charge storing memory cell structure.

Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.

Abstract: A method for manufacturing a memory cell in accordance with various embodiments may include: forming at least one charge storing memory cell structure over a substrate, the charge storing memory cell structure having a first sidewall and a second sidewall opposite the first sidewall; forming an electrically conductive layer over the substrate and the charge storing memory cell structure; patterning the electrically conductive layer to form a spacer at the first sidewall and a blocking structure at the second sidewall of the charge storing memory cell structure; implanting first dopant atoms to form a first doped region in the substrate proximate the spacer, wherein the first dopant atoms are blocked by the blocking structure; removing the blocking structure after implanting the first dopant atoms; implanting second dopant atoms to form a second doped region in the substrate proximate the second sidewall of the charge storing memory cell structure.

Abstract: In an embodiment, an apparatus includes a source region, a gate region and a drain region supported by a substrate, and a drift region including a plurality of vertically extending n-wells and p-wells to couple the gate region and the drain region of a transistor, wherein the plurality of n-wells and p-wells are formed in alternating longitudinal rows to form a superjunction drift region longitudinally extending between the gate region and the drain region of the transistor.

Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.

Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.

Abstract: One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material.

Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.

Abstract: In an embodiment, an apparatus includes a source region, a gate region and a drain region supported by a substrate, and a drift region including a plurality of vertically extending n-wells and p-wells to couple the gate region and the drain region of a transistor, wherein the plurality of n-wells and p-wells are formed in alternating longitudinal rows to form a superjunction drift region longitudinally extending between the gate region and the drain region of the transistor.

Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.