Patents by Inventor Martin T. Rowland
Martin T. Rowland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10372197Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.Type: GrantFiled: December 2, 2016Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
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Patent number: 10345884Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: GrantFiled: August 16, 2016Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don C. Soltis, Jr., Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Patent number: 9977482Abstract: An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.Type: GrantFiled: December 21, 2011Date of Patent: May 22, 2018Assignee: Intel CorporationInventors: Ankush Varma, Ian M. Steiner, Krishnakanth V. Sistla, Matthew M. Bace, Vivek Garg, Martin T. Rowland, Jeffrey S. Wilder
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Publication number: 20170115716Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: ApplicationFiled: August 16, 2016Publication date: April 27, 2017Inventors: ANKUSH VARMA, KRISHNAKANTH V. SISTLA, MARTIN T. ROWLAND, CHRIS POIRIER, ERIC J. DEHAEMER, AVINASH N. ANANTHAKRISHNAN, JEREMY J. SHRALL, XIUTING C. MAN, STEPHEN H. GUNTHER, KRISHNA K. RANGAN, DEVADATTA V. BODAS, DON SOLTIS, HANG T. NGUYEN, CYPRIAN W. WOO, THI DANG
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Patent number: 9606595Abstract: Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system.Type: GrantFiled: December 30, 2011Date of Patent: March 28, 2017Assignee: Intel CorporationInventors: Ankush Varma, Jeremy J. Shrall, Krishnakanth Venkata Sistla, Avinash N. Ananthakrishnan, Vivek Garg, Christopher A. Poirier, Sr., Martin T. Rowland, Edward R. Stanford
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Publication number: 20170083076Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.Type: ApplicationFiled: December 2, 2016Publication date: March 23, 2017Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
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Patent number: 9557804Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.Type: GrantFiled: September 28, 2015Date of Patent: January 31, 2017Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Cesar A. Quiroz, Vivek Garg, Martin T. Rowland, Inder M. Sodhi, James S. Burns
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Patent number: 9547027Abstract: In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.Type: GrantFiled: March 30, 2012Date of Patent: January 17, 2017Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Vivek Garg, James S. Burns
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Patent number: 9535487Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.Type: GrantFiled: September 16, 2015Date of Patent: January 3, 2017Assignee: Intel CorporationInventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
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Patent number: 9417681Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: GrantFiled: April 27, 2015Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Patent number: 9405351Abstract: In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.Type: GrantFiled: December 17, 2012Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Ian M. Steiner, Vivek Garg, Chris Poirier, Martin T. Rowland
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Patent number: 9268393Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.Type: GrantFiled: November 30, 2012Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth Sistla, Martin T. Rowland, Brian J. Griffith, Viktor D. Vogman, Joseph R. Doucette, Eric J. Dehaemer, Vivek Garg, Chris Poirier, Jeremy J. Shrall, Avinash N. Ananthakrishnan, Stephen H. Gunther
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Publication number: 20160018883Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.Type: ApplicationFiled: September 28, 2015Publication date: January 21, 2016Inventors: Ankush VARMA, Krishnakanth V. SISTLA, Cesar A. QUIROZ, Vivek GARG, Martin T. ROWLAND, Inder M. SODHI, James S. BURNS
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Publication number: 20160004291Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.Type: ApplicationFiled: September 16, 2015Publication date: January 7, 2016Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
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Patent number: 9170624Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.Type: GrantFiled: March 1, 2013Date of Patent: October 27, 2015Assignee: Intel CorporationInventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
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Patent number: 9158351Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.Type: GrantFiled: March 29, 2012Date of Patent: October 13, 2015Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Cesar A. Quiroz, Vivek Garg, Martin T. Rowland, Inder M. Sodhi, James S. Burns
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Patent number: 9141166Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.Type: GrantFiled: December 13, 2011Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Krishnakanth V. Sistla, Martin T. Rowland, Cesar A. Quiroz, Joseph R. Doucette, Gopikrishna Jandhyala, Kai Cheng, Celeste M. Brown, Avinash N. Ananthakrishnan
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Publication number: 20150241949Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: ApplicationFiled: April 27, 2015Publication date: August 27, 2015Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Patent number: 9098261Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.Type: GrantFiled: December 15, 2011Date of Patent: August 4, 2015Assignee: Intel CorporationInventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
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Patent number: 9037840Abstract: An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.Type: GrantFiled: June 29, 2012Date of Patent: May 19, 2015Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang