Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.

Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.

Abstract: The present disclosure provides systems and techniques in which an ambient may be controlled on the basis of a current status of a micro-processed substrate so as to maintain the status within predefined limits. In illustrative embodiments, the substrate may be stored in an ambient, for which temperature and/or contents of one or more gaseous species may be controlled so as to reduce the change of status. Consequently, in particular, queue times may be significantly prolonged, thereby imparting superior flexibility to scheduling the overall process flow in a complex manufacturing environment.

Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract: A method for forming a transistor device is disclosed that includes forming a first gate electrode on a substrate, forming a nitride layer, in particular an SiN layer, over the first gate electrode and forming a first strained layer over the nitride layer, in particular the SiN layer. A transistor device is also disclosed that includes a first gate electrode, a nitride layer, in particular an SiN layer, formed over the first gate electrode and a first strained layer formed over the nitride layer, in particular the SiN layer.

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract: A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

Abstract: The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer.

Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

Abstract: A semiconductor structure includes a resistor. The resistor includes a semiconductor region, a dielectric layer, a first electrical connection and a second electrical connection. The dielectric layer is provided on the semiconductor region and includes a high-k material having a greater dielectric constant than silicon dioxide. The dielectric layer includes a species creating fixed charges. A first electrical connection is provided at a first end of the semiconductor region and a second electrical connection is provided at a second end of the semiconductor region.

Abstract: The concentration of a non-silicon species in a semiconductor alloy, such as a silicon/germanium alloy, may be increased after a selective epitaxial growth process by oxidizing a portion of the semiconductor alloy and removing the oxidized portion. During the oxidation, preferably the silicon species may react to form a silicon dioxide material while the germanium species may be driven into the remaining semiconductor alloy, thereby increasing the concentration thereof. Consequently, the threshold adjustment of sophisticated transistors may be accomplished with enhanced process uniformity on the basis of a given parameter setting for the epitaxial growth process while nevertheless providing a high degree of flexibility in adjusting the composition of the threshold adjusting material.

Abstract: When forming high-k metal gate electrode structures by providing the gate dielectric material in an early manufacturing stage, the heat treatment or anneal process may be applied after incorporating work function metal species and prior to capping the gate dielectric material with a metal-containing electrode material. In this manner, the CET for a given physical thickness for the gate dielectric layer may be significantly reduced.

Abstract: A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

Abstract: Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles.