Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract: The memory cell is arranged in a ridge of semiconductor material forming a fin with sidewalls and a channel region between source and drain regions. Memory layer sequences provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of ridges at a distance parallel to one another and have sidewalls facing a neighboring ridge form an array of charge-trapping memory cells. Wordlines are arranged between the ridges, sections of the wordlines forming the gate electrodes. This arrangement enables a double gate operation of the cells and thus allows for a storage of four bits of information in every single memory cell structure.

Abstract: A method is used for processing a structure of a semiconductor component. The structure has at least one partial structure to be etched, in particular a sublithographic partial structure. The at least one partial structure has at least one structure to be etched with at least one lateral etch stop to which at least one mask is applied in such a way that at least one lateral etch stop is covered by the mask and afterward at least one of the structures to be etched is etched away isotropically as far as at least one etch stop using the mask. The at least one mask and the at least one etch stop are then removed.

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract: The hydrodynamic effects—which occur during immersion lithography as a result of the movement of the semiconductor wafer—in a liquid preferably provided between the last lens surface of the projection system and the semiconductor wafer can be avoided by means of a movable illumination region for illuminating a cutout of a mask containing a structure to that can be imaged onto the semiconductor wafer. A scan movement of the mask and the semiconductor wafer can be either reduced or entirely avoided by means of a movement of the illumination region.

Abstract: A nonvolatile memory element includes a first material region, a second material and an oxidation material region including an oxidation material as a memory material region. The oxidation material includes an oxidized form of the first material and/or an oxidized form of the second material. The first material is selected such that its oxidized form is formed in comparatively high-resistance fashion. The second material is selected such that its oxidized form is formed in comparatively low-resistance fashion.

Abstract: In a charge trapping memory cell, programming occurs by trapping hot electrons from the channel region in a storage layer. The erasure occurs by Fowler-Nordheim tunneling of the electrons through the lower boundary layer to source or drain or preferably through the upper boundary layer into the gate electrode. The boundary layers are preferably aluminum oxide.

Abstract: Provided is a method for fabricating self-assembled regions of silicon as well as semiconductor memory cells based thereon. By structuring a layer of silicon prior to thermal formation of the self-assembled regions under vacuum conditions control of location of these regions is achieved. A chargeable self-assembled region of silicon acts as a floating gate of a quantum dot DRAM including a control gate, a channel region within a semiconductor substrate and source and drain regions formed therein.

Abstract: Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to first and second bit lines. Word lines are arranged above the first and second bit lines and connected to rows of gate electrodes. The vertical transistor structure facilitates a further shrinking of the cells and enables a required minimum effective channel length.

Abstract: An oxide layer, a nitride layer, and a layer of amorphous silicon are applied to a surface of a semiconductor substrate. A resist mask is applied and implantations are performed to form doped regions of source and drain and doped regions within the amorphous silicon layer. The resist mask and undoped parts of the amorphous silicon are removed to form a silicon mask. The silicon mask is applied to etch back the nitride layer. After a removal of the silicon mask, the nitride is oxidized to form an oxide-nitride-oxide layer sequence, which is laterally restricted to the area above the source/drain regions.

Abstract: The memory cell is arranged in a ridge of semiconductor material forming a fin with sidewalls and a channel region between source and drain regions. Memory layer sequences provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of ridges at a distance parallel to one another and have sidewalls facing a neighboring ridge form an array of charge-trapping memory cells. Wordlines are arranged between the ridges, sections of the wordlines forming the gate electrodes. This arrangement enables a double gate operation of the cells and thus allows for a storage of four bits of information in every single memory cell structure.

Abstract: The channel region is slightly elevated with respect to the source and drain regions to form steps in the semiconductor surface, which are covered by a dielectric memory layer sequence provided for charge-trapping, the memory layer sequence comprising a lower confinement layer, a memory layer and an upper confinement layer. Electrons that are accelerated from source to drain are more probably scattered on a straight trajectory, on which they pass the lower confinement layer and are trapped in the memory layer. This memory cell aims at improving the speed of write operations.

Abstract: Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to first and second bit lines. Word lines are arranged above the first and second bit lines and connected to rows of gate electrodes. The vertical transistor structure facilitates a further shrinking of the cells and enables a required minimum effective channel length.

Abstract: The hydrodynamic effects—which occur during immersion lithography as a result of the movement of the semiconductor wafer—in a liquid preferably provided between the last lens surface of the projection system and the semiconductor wafer can be avoided by means of a movable illumination region for illuminating a cutout of a mask containing a structure to that can be imaged onto the semiconductor wafer. A scan movement of the mask and the semiconductor wafer can be either reduced or entirely avoided by means of a movement of the illumination region.

Abstract: In a charge trapping memory cell, programming occurs by trapping hot electrons from the channel region in a storage layer. The erasure occurs by Fowler-Nordheim tunneling of the electrons through the lower boundary layer to source or drain or preferably through the upper boundary layer into the gate electrode. The boundary layers are preferably aluminum oxide.