Abstract: An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.

Abstract: A circuit includes a voltage supply net, a first capacitor connected between the voltage supply net and a reference potential via a first transistor, and a second capacitor connected between the voltage supply net and the reference potential via a second transistor, such that the first and the second capacitor form at least a part of a support capacitance for the voltage supply net. The circuit is configured to provide control signals to control terminals of the first and second transistor such that the first transistor allows for a limited current flow in case of a shortage of the first capacitor and such that the second transistor allows for a limited current flow in case of a shortage of the second capacitor.

Abstract: A device for accessing a logical content of a memory cell, the memory cell including a cell capacity for storing a charge related to the logical content, wherein the cell capacity is connected between a bit line having a bit line capacity and a reference potential, the device including: a reference node having a reference capacity being smaller than the bit line capacity; and a circuit for changing a potential of the bit line and the reference node, respectively, in case of a read or write access of the memory cell, wherein the change of the potential of the bit line is conducted with a first current and the change of the potential of the reference node is conducted with a second current, wherein the first current is greater than the second current.

Abstract: A device for accessing a logical content of a memory cell, the memory cell including a cell capacity for storing a charge related to the logical content, wherein the cell capacity is connected between a bit line having a bit line capacity and a reference potential, the device including: a reference node having a reference capacity being smaller than the bit line capacity; and a circuit for changing a potential of the bit line and the reference node, respectively, in case of a read or write access of the memory cell, wherein the change of the potential of the bit line is conducted with a first current and the change of the potential of the reference node is conducted with a second current, wherein the first current is greater than the second current.

Abstract: A memory circuit includes a plurality of bit lines and a plurality of memory cells which may be written to via a respective bit line. The memory circuit further includes a bit line control circuit. The bit line control circuit is configured to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected.

Abstract: The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit carrier. According to the method, a respective prescribed test signal is applied to each internal line of the component using a controllable test signal generator integrated in the component. Output signals applied to the connections of the circuit carrier are tapped off. Thereafter, the respective output signals tapped off are identified with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the wire configuration between the component connections and circuit carrier connections.

Abstract: An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.

Abstract: A method and apparatus for reducing power consumption of a memory device. The method includes initiating a precharge operation. The precharge operation includes driving one or more bitlines to a precharge voltage. The method also includes identifying one or more defective wordlines and, during the precharge operation, driving the identified defective word lines to the precharge voltage.

Abstract: Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

Abstract: A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.

Abstract: The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line (103) for forwarding internal data (105) in the electronic circuit unit (101) and at least one data connection line (104) for outputting the internal data from the electronic circuit unit (101) and for inputting external data (106) into the electronic circuit unit (101). A changeover unit (102), which is intended to change over the data connection line (104) either to the internal data line (103) or to internal signal lines (113), and a combinational logic unit (111) for combining an initialization signal (109), which is provided by the electronic circuit unit (101) to be monitored, with an external changeover signal (108), which is supplied via a changeover signal input (107) of the electronic circuit unit (101) to be monitored, are also provided.

Abstract: A testing system has a processor, a module and at least one manufactured semiconductor device. The processor is configured to send and receive testing signals. The module is electrically coupled to the processor. The at least one manufactured semiconductor device is mounted on the module, and the semiconductor device has a plurality of pins at least one of which is a non-functional pin. The system is configured to provide the processor access to the semiconductor device. An external device monitors voltage at the non-functional pin of the semiconductor device.

Abstract: A system and method for testing a memory device is disclosed. One embodiment includes a plurality of memory cells. Each of the memory cells can be controlled by an address. A test memory for storing test results is provided. An address comparing unit is configured to determine whether the address of a memory cell lies in a predetermined address space. A controllable unit for storing test results is connected with the test memory and the address comparing unit. The controllable unit is controlled by the address comparing unit such that error information of the tested memory cell is only stored in the test memory if the address of the tested memory cell lies in the selected address space.

Abstract: Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

Abstract: A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.

Abstract: A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.

Abstract: A test mode for component-specific testing of a memory module. Data is written to and stored in each memory component of a memory module, which data indicates whether the memory component is to execute a particular test mode. Upon receiving a test mode command supplied in common to all of the memory components on the memory module, each memory component examines the data to determine whether it is to execute a test mode command supplied contemporaneously therewith or subsequently supplied test mode commands.

Abstract: An integrated semiconductor memory has regular row and column lines, which can be replaced with redundant row and column lines in the event of a fault. Following initialization of the memory cells with an initialization data item, a data generator circuit writes an identification data item to the memory cells along a regular row or column line. A faulty regular row or column line is replaced with the associated redundant row or column line. Next, the initialization data item is written to memory cells along sound regular row or column lines and the respective identification data item is written to the memory cells along a faulty regular row or column line. Faulty regular row or column lines have the same data value in their memory cells as the redundant row or column lines replacing them.

Abstract: Embodiments of the present inventions provide a method and apparatus for reducing power consumption of a memory device. In one embodiment, the method includes initiating a precharge operation. The precharge operation includes driving one or more bitlines to a precharge voltage. The method also includes identifying one or more defective wordlines and, during the precharge operation, driving the identified defective wordlines to the precharge voltage.

Abstract: A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.