Abstract: An apparatus is provided for converting the form in which a synchronisation request for a barrier synchronisation is provided. The synchronisation request is provided from a first synchronisation circuitry to a second synchronisation circuitry by asserting one of a set of separate signals that may each correspond to a bit in a register or a signal on a wire. The second synchronisation circuitry provides for the packetisation of the sync request by sending a packet comprising the sync request over a network to be received at a further subsystem.

Abstract: The same test data frame is dispatched from a network interface device a plurality of times so as to test a network. Since the same test data frame is used, it may be unnecessary for a new test data frame to be provided and protocol processed each time one is required to be sent. The protocol processing resources of the network interface device are then available for sending further traffic in parallel with the dispatch of the test data frames. On the receive side, the network interface device collects statistics regarding the reliable receipt of test frames, without requiring the test frames to be further processed and provided to a driver of the network interface device. In this way, the processing and buffering capacity in the network interface device is available for handling further traffic in parallel with the test traffic.

Abstract: An apparatus is provided for converting the form in which a synchronisation request for a barrier synchronisation is provided. The synchronisation request is provided from a first synchronisation circuitry to a second synchronisation circuitry by asserting one of a set of separate signals that may each correspond to a bit in a register or a signal on a wire. The second synchronisation circuitry provides for the packetisation of the sync request by sending a packet comprising the sync request over a network to be received at a further subsystem.

Abstract: A receiver, for example a receiver of broadcast digital terrestrial television signals modulated using COFDM (Coded Orthogonal Frequency Division Multiplexing), imposes a phase adjustment on a received signal. Phase adjustment may be effected, for example, by sample alignment of the signal, such as for cyclic prefix removal, or by shifting a window setting for a Fast Fourier Transform (FFT) processor. Before channel estimation or decoding is performed on the information stream, the information stream is derotated to compensate for the phase adjustment previously imposed on the received signal.

Abstract: A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

Abstract: A system and a method are presented for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, wherein the a first number M of clock pulses related to the at least one clock signal within a predefined cycle period is counted and the counted first number M of clock pulses is compared with a reference number. Depending on the result of the comparison the presence of the at least one clock signal is detected or not.

Abstract: A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

Abstract: A receiver, for example a receiver of broadcast digital terrestrial television signals modulated using COFDM (Coded Orthogonal Frequency Division Multiplexing), imposes a phase adjustment on a received signal. Phase adjustment may be effected, for example, by sample alignment of the signal, such as for cyclic prefix removal, or by shifting a window setting for a Fast Fourier Transform (FFT) processor. Before channel estimation or decoding is performed on the information stream, the information stream is derotated to compensate for the phase adjustment previously imposed on the received signal.