Patents by Inventor Martin W. Popp

Martin W. Popp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250022882
    Abstract: A semiconductor device including a complementary metal-oxide-semiconductor (CMOS) device that includes a P-Well region including a P-Well, a first shallow trench isolation (STI) region that is disposed on a frontside surface of the CMOS device and above the P-Well, and a first deep trench isolation (DTI) region that is disposed under the first STI region and that extends to a backside surface of the CMOS device, the first DTI region completely surrounding the P-Well, and a N-Well region adjacent to the P-Well region, the N-Well region including a N-Well, a second STI region disposed on the frontside surface of the CMOS device and above the N-Well, and a second DTI region that is disposed under the second STI region and that extends to the backside of the CMOS device, the second DTI region completely surrounding the N-Well; and a secondary device bonded to the CMOS device.
    Type: Application
    Filed: July 10, 2024
    Publication date: January 16, 2025
    Inventors: Martin W. Popp, Zia A. Shafi
  • Publication number: 20240428859
    Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.
    Type: Application
    Filed: September 10, 2024
    Publication date: December 26, 2024
    Inventors: Michael A. Smith, Martin W. Popp
  • Patent number: 12112804
    Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.
    Type: Grant
    Filed: August 23, 2023
    Date of Patent: October 8, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Smith, Martin W. Popp
  • Publication number: 20240290385
    Abstract: A microelectronic device comprises, a control circuitry structure comprising an active region including control logic circuitry at least partially within a semiconductive material; a bond pad on a backside of the control circuitry structure; a conductive contact vertically extending from the bond pad, through the semiconductive material, and to the control logic circuitry; and a dielectric-filled slit vertically extending into the semiconductive material and horizontally circumscribing the conductive contact, portions of the semiconductive material horizontally interposed between the conductive contact and the dielectric-filled slit. Additional microelectronic devices, memory devices, microelectronic device packages, and electronic systems are also described.
    Type: Application
    Filed: January 10, 2024
    Publication date: August 29, 2024
    Inventors: James E. Davis, Shyam Surthi, Martin W. Popp, KangYoul Lee, Yui Shimizu
  • Publication number: 20240274533
    Abstract: A semiconductor device assembly including a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines being connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding string driver, wherein a backside surface of the first wafer is bonded to a frontside surface of the second wafer to form a wafer-on-wafer (WOW) bonding.
    Type: Application
    Filed: January 18, 2024
    Publication date: August 15, 2024
    Inventors: Michael A. Smith, Martin W. Popp, Richard J. Hill
  • Publication number: 20230395151
    Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 7, 2023
    Inventors: Michael A. Smith, Martin W. Popp
  • Patent number: 11783896
    Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Smith, Martin W. Popp
  • Publication number: 20230050443
    Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 16, 2023
    Inventors: Michael A. Smith, Martin W. Popp