Abstract: A circuit for processing an input audio signal received at an input of the circuit provides a processed audio signal at a circuit output. The circuit includes first and second conductive paths through which the received audio signal travels. The audio signal is processed such that harmonics of the signal components with a low-frequency are generated in the second path and are admixed to the signal in the first path. In the second path the audio signal is sequentially bandpass filtered, weighted with a correction factor, amplified, limited to a predetermined value, and bandpass filtered, where the correction factor is reduced when the predetermined value is exceeded.

Abstract: Audio source selection circuit (QW) for an audio signal processor with inputs for source signals (F1, F2, NA, NB) provided by at least one source (Q1, Q2), with a processing device (V) which forms pairs of signals from the source signals, with a settable source selection logic (Qs) to which the channels of the processing device (V) are applied, and with outputs coupled to signal outputs of the settable source selection logic (Qs) and each forming an output channel (Co1, Co2, Co3), the processing device (V) including an automatic audio mode setting device which generates suitable intermediate channels (Cz1, Cz2, Cz3, Cz4) from the source signals (F1, F2, NA, NB) according to a source- and application-related mode.

Abstract: An integrated circuit for decoding an analog audio signal includes a tuner that receives the analog audio signal and provides a sound intercarrier frequency signal. A digital demodulator receives and digitizes the sound intercarrier frequency signal to provide a digitized sound intercarrier frequency signal, and digitally demodulates the digitized sound intercarrier frequency signal to provide a digitized multichannel television sound (MTS) demodulated signal. A digital broadcast television system committee (BTSC) compatible decoder receives and decodes the digitized multichannel television sound (MTS) demodulated signal, and provides a summed (L+R) audio output signal and a difference (L−R) audio output signal.

Abstract: During the manufacture of a television receiver or a video recorder in which data signals encoded by the BTSC standard are decoded, a precise adjustment is necessary because of parts tolerances.

Abstract: Carrier generation facility for a switchable digital demodulator (D) of digital MPX signals (mpx1) with associated pilot signal (p1) which are locked to an arbitrary clock signal (t1). A pilot signal PLL (10) generates a first carrier signal (x1.1, x2.1) and a second carrier signal (x1.2) by means of a first value allocator (15) and a second value allocator (20), respectively. According to the MPX signal (mpx1) to be demodulated, a control device (60) delivers a start value (i0) and at least one phase correction value (k1, k2). The start value (i0) sets the capture range of the pilot signal PLL (10) for the pilot signal (p1) according to the respective standard. In a first correcting device (16) and/or a second correcting device (23), the phase correction values (k1, k2) correct the system-inherent phase deviations of the first carrier signal (x1.1, x2.1) and/or the second carrier signal (x1.2).

Abstract: An integrated circuit for decoding an analog audio signal includes a tuner that receives the analog audio signal and provides a sound intercarrier frequency signal. A digital demodulator receives and digitizes the sound intercarrier frequency signal to provide a digitized sound intercarrier frequency signal, and digitally demodulates the digitized sound intercarrier frequency signal to provide a digitized multichannel television sound (MTS) demodulated signal. A digital broadcast television system committee (BTSC) compatible decoder receives and decodes the digitized multichannel television sound (MTS) demodulated signal, and provides a summed (L+R) audio output signal and a difference (L−R) audio output signal.

Abstract: A digital sound processor for processing multiple standard sound signals and including an audio source which is connected to a digital control input of the sound processor and generates, via externally or internally applied control signals, an audible signal or an audible signal sequence which is fed via the output devices of the sound processor to reproducers.

Abstract: A stereophonic sound system is disclosed, having a source of stereophonic signals which contain a right signal and a left signal as well as further signals which supplement the right and left signals to convey a three-dimensional sound impression. The right and left signals are adapted to a stereo base of a pair of loudspeakers having a correspondingly small size by means of a modification circuit. Of the stereophonic signals, only the right and left signals are fed to the modification circuit so that they are falsified as little as possible. An improved system for conveying a three-dimensional sound impression is thus provided.

Abstract: The invention relates to a digital signal processor with a RAM (random-access memory) having its output connected to a first input and, through a first temporary storage device to a second input of a multiplier, with an adder following the multiplier, and with a clock device for controlling data-word transfers. The speed of the processor is increased by connecting a second auxiliary storage device between the RAM and the first input of the multiplier and providing a first switching element via which the RAM and the second temporary storage device are connectable to the first input of the multiplier.

Abstract: A circuit is disclosed for modifying a first signal and a second signal from a signal source providing at least two signals. The circuit including devices for forming signal components from the first and second signals. The signal components are then combined into a modified first signal and a modified second signal by means of a first combining device and a second combining device, respectively.

Abstract: An improved method for digital interpolation of signals for a second interpolation filter is disclosed which permits a high signal/noise ratio with a minimum amount of circuitry for an overall system comprising first and second interpolation filters. The method for digital interpolation of signals requires multiplying delayed input values locked to a first signal by corresponding weighting factors which are dependent on a time-difference value determined by the interpolating instant and the time grid of the first clock signal. The weighting factors are determined by an impulse response in the time domain. The associated transfer function has an attenuation characteristic in the frequency domain which, with respect to the stop bands, is limited essentially to the alias regions located at the frequency multiples of the first clock signal.

Abstract: Method and apparatus for active noise suppression in stereo multiplex signals particularly in an automotive radio receiver includes an insertion circuit where the disturbed signal section is replaced with an insertion signal formed by sampled signal values/signal sections which are located before and/or after the disturbed signal section. Basic-delay stages ensure that only those sample values are used for the insertion signal which are separated from the respective instant of insertion by a time interval having an integral relationship nT to the period T of a carrier contained in the stereo multiplex signal (where n is a positive integer).

Abstract: A digital phase-locked loop has a periodically overflowing digital oscillator (DCO), implemented as a modulo adder, and a processor device. The processor device adjusts the period T of the digital oscillator to a nominal period, determined from periodically occurring synchronizing pulses, by comparing the actual phase of the digital oscillator with a set phase at the control clock rate of the periodic synchronizing pulses. After the digital oscillator has been locked to the nominal period, the processor device compares the phases by using a double-frequency signal sequence of one-half line period derived from the digital oscillator output signal. The DCO output signal is fed to a correction device where an address-phase signal, locked to the DCO output signal, is generated so that when a non-periodic synchronizing pulse occurs, the address-phase signal is shifted by one period of the signal sequence of one-half line period with respect to the digital oscillator output signal.

Abstract: An improved digital video signal processing circuit, for common use in the recording and playback modes of a video tape recorder, has a chrominance processing circuit for processing the chrominance signal of the input digital composite video signal through a first baseband mixer, a chrominance processor, and a second baseband mixer, and a luminance processing circuit for frequency modulating/demodulating the luminance signal, so that the processed chrominance and luminance signals can be added together to form an output digital composite video signal. The improved digital circuit automatically regulates the frequencies of the mixing signals for both mixers using line stepping signals obtained from a horizontal line sweep generator in the luminance processing circuit. The possibility of phase errors is eliminated, and quadrature errors in the chrominance signal are prevented.

Abstract: In a frequency modulation system, a modulating signal is split into its low-frequency and high-frequency components. The low frequency component is used to modulate a carrier signal by conventional means in a first circuit and the low- and high-frequency components are used to narrowband modulate the carrier signal in a second circuit. The outputs of the first and second circuits are combined to provide a frequency modulated signal. The modulating and carrier signals can be binary-coded signals.

Abstract: A central processor for digital signal processing operates at a high clock rate. In the central processor, data is transferred and processed largely in parallel and simultaneously. A buffer is inserted in the data link between a data memory and an ALU by means of at least three data buses so that within one clock period, all necessary data transfers for a two-address operation of the ALU are performed by using the buffer. In particular, a unidirectional data bus and a bidirectional data bus transfer data from the buffer to the ALU, and the bidirectional data bus transfers the result of an ALU operation back to the buffer. Simultaneously with the transfers between the buffer and the ALU, a data transfer is performed between the data memory and the buffer. The data transfers and the data processing are controlled by a control unit in which a fixed program is stored segment by segment. The use of pipelining in the control unit permits a high processing speed.

Abstract: To realize the transfer function in a digital filter circuit:H(z)=b(1-z.sup.-kn)(1-z.sup.-n).sup.m-1 /(1-z.sup.-).sup.m,the following sections are cascaded: a multiplier for multiplying by 2.sup.-q ; m-1 integrators, each including a delay element which provides a delay equal to the period of the input sampling frequency; and mth integrator including a delay element which is reset by the output sampling clock; a sampling device which is switched at the output sampling clock rate; m-2 differentiators, each including a delay element which provides a delay equal to the period of the output sampling clock; and an (m-1)st differentiator including k delay elements which each provide a delay equal to the period of the output sampling clock.