Abstract: A method for fabricating and checking at least two structures of an electronic circuit in a semiconductor substrate. By using two different masks, in two method steps, identical configurations of first and second structures are produced in useful areas of the semiconductor substrate. In the scribe lines, bordering the useful area, only first structures are produced using the first mask and only second structures are produced using the second mask.

Abstract: A configuration for voltage buffering in dynamic memories based on CMOS technology uses the capacitance of a well structure for buffering the amplified word line voltage or the negative word line reverse voltage.

Abstract: A method for fabricating and checking at least two structures of an electronic circuit in a semiconductor substrate. By using two different masks, in two method steps, identical configurations of first and second structures are produced in useful areas of the semiconductor substrate. In the scribe lines, bordering the useful area, only first structures are produced using the first mask and only second structures are produced using the second mask.

Abstract: The digital memory has at least one data line and address lines. It also has a switching unit that, in an active state, inverts signals on the data line or on at least one of the address lines and that, in an inactive state, leaves the signals unchanged. In a first operating mode, the switching unit is in the same state for writing and reading. In a second operating mode, the switching unit is in respectively opposite states for writing and for reading.

Abstract: The invention relates to a method for reading and refreshing data contents of a dynamic semiconductor memory having many volatile memory cells disposed in columns and rows in a matrix. The reading of the data contents from addressed memory cells is done with the aid of at least two data buses. The data contents are applied word by word to the data buses and a refreshing of the data contents of the memory cells is effected by a refresh pulse. According to the invention, it is provided that the data words applied to the data buses after the triggering of the refresh pulse are maintained for a predetermined period of time on all the data buses and only after that are the data words removed by of a shutoff pulse.

Abstract: An integrated buffer circuit configuration has two inverters which are mutually connected in series. A circuit node lies between the two inverters. At least the first inverter is a CMOS inverter for an input signal IN. The CMOS inverter has an n-channel transistor which is connected to a first supply potential. The source of a p-channel transistor is connected with a constant current source. A first enable transistor is connected between the n-channel transistor of the first inverter and the circuit node. A second enable transistor is connected in parallel to the configuration formed by the constant current source and the p-channel transistor of the first inverter. The gates of the enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS-transistor may function as the constant current source.

Abstract: An integrated buffer circuit configuration has two inverters which are mutually connected in series. The first inverter includes an n-channel transistor and a constant current source. The source of the n-channel transistor is connected to a first supply potential. The drain of the transistor is connected with the constant current source through a first enable transistor. A second enable transistor is connected parallel to the constant current source. The gates of enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS transistor may function as the constant current source. The MOS transistor is then connected to a second supply potential and its gate lies at reference potential with a value with always has a constant difference with respect to the second supply potential. During operation, the MOS transistor is conducting.