Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.

Abstract: A computer-implemented method for automated generation of test layouts for verifying a DRC deck. The method comprises receiving a first layout (L1) comprising one or more polygon shapes (P1) defined by a plurality of polygon parameters (W1,H1). Design rules (R1,R2) are received comprising inequality constraints (C) on the polygon parameters (W1,H1). A second layout (L2) is calculated by applying a random change (?W12) of value to at least one of the polygon parameters (W1) of the first layout (L1). A third layout (L3) is calculated by varying values of the polygon parameters (W1,H1) of the second layout (L2) until a respective slack (S1,S2) of the polygon parameters (W1,H1) with respect to one or more of the parameter boundaries (B1,B2) defined by the constraints is minimized. The third layout (L3) may be stored as candidate test layout.

Abstract: A computer-implemented method for automated generation of test layouts for verifying a DRC deck. The method comprises receiving a first layout (L1) comprising one or more polygon shapes (P1) defined by a plurality of polygon parameters (W1,H1). Design rules (R1,R2) are received comprising inequality constraints (C) on the polygon parameters (W1,H1). A second lay-out (L2) is calculated by applying a random change (?W12) of value to at least one of the polygon parameters (W1) of the first layout (L1). A third layout (L3) is calculated by varying values of the polygon parameters (W1,H1) of the second layout (L2) until a respective slack (S1,S2) of the polygon parameters (W1,H1) with respect to one or more of the parameter boundaries (B1,B2) defined by the constraints is minimized The third layout (L3) may be stored as candidate test layout.

Abstract: There is provided a computer-implemented method for verification of a layout of an integrated circuit according to a design intent with a selected manufacturing process. The method comprises defining corner points of a first circuit part 1 as seed points 3, projecting a specifically designed polygon shape 4 proximal to a seed point 3 and calculating an overlap area 5 between the projected polygon shape 4 and a second circuit part 2. The layout is rejected when the overlap area does not conform to a threshold overlap area determined by the design intent.

Abstract: There is provided a computer-implemented method for verification of a layout of an integrated circuit according to a design intent with a selected manufacturing process. The method comprises defining corner points of a first circuit part 1 as seed points 3, projecting a specifically designed polygon shape 4 proximal to a seed point 3 and calculating an overlap area 5 between the projected polygon shape 4 and a second circuit part 2. The layout is rejected when the overlap area does not conform to a threshold overlap area determined by the design intent.

Abstract: The invention relates to a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. The layout is comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other. An initial set of illumination conditions is provided and a plurality of polygon patterns requiring illumination conditions critical for circuit functionality. For the initial set of illumination conditions a local cost number is calculated, defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition. For each polygon pattern the cost numbers are aggregated; and the illumination conditions are varied so as to select an optimal set of illumination conditions having an optimized aggregated cost number.

Abstract: The invention relates to a method of optimizing an integrated circuit layout, wherein an initial integrated circuit layout is provided. A predetermined set of physical characteristics of a predetermined set of polygons of said initial circuit layout, is assessed and said physical characteristics are aggregated to derive an integral quality number associated to said initial circuit layout. According to the invention, cost functions are generated to evaluate a perturbed quality number of said perturbed layout and layout perturbations are selected that optimize the quality number, so that the circuit layout is optimized.

Abstract: The invention relates to a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. The layout is comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other. An initial set of illumination conditions is provided and a plurality of polygon patterns requiring illumination conditions critical for circuit functionality. For the initial set of illumination conditions a local cost number is calculated, defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition. For each polygon pattern the cost numbers are aggregated; and the illumination conditions are varied so as to select an optimal set of illumination conditions having an optimized aggregated cost number.

Abstract: The invention relates to a method of optimizing an integrated circuit layout, wherein an initial integrated circuit layout is provided. A predetermined set of physical characteristics of a predetermined set of polygons of said initial circuit layout, is assessed and said physical characteristics are aggregated to derive an integral quality number associated to said initial circuit layout. According to the invention, cost functions are generated to evaluate a perturbed quality number of said perturbed layout and layout perturbations are selected that optimize the quality number, so that the circuit layout is optimized.