Abstract: A system and method for compiling a computer program, and software for performing such compilation, are provided, the compilation process determining where to store the computer program in memory for subsequent retrieval by a data processing apparatus that is to execute the computer program. The method can be used to compile a computer program for execution on the data processing apparatus having memory comprising a plurality of memory sections, each memory section having a record associated therewith identifying one or more access properties associated with that memory section.

Abstract: An interface operable to request instructions from a data store storing instructions of an application to be processed by a data processor, and operable to receive and transmit said instructions to said data processor, said interface comprising: an input operable to receive said instructions from said data store via at least one input bus; a buffer operable to store said received instructions; an output operable to output said instructions to said data processing apparatus via at least one output bus; a control signal input operable to receive a control signal; and a buffer controller operable to: control said buffer to request an instruction subsequent to a previously received instruction within an instruction stream of said application from said data store in response to detection of no control signal on said control signal input and to detection of available buffer storage capacity; and in response to a control signal received at said control signal input, said controller is operable to control at least on

Abstract: A data processing apparatus comprises data processing logic operable to perform data processing operations specified by program instructions. The data processing logic (140) has a plurality of functional units (142, 144, 146) configured to execute in parallel on data received from a data source. A decoder (130) is responsive to a single program instruction to control the data processing logic (140) to concurrently execute the single program instruction on each of a plurality of vector elements of each of a respective plurality of vector input operands (310, 320) received from the data source using the plurality of functional units (142, 144, 146).

Abstract: A direct memory access controller is provided that is operable to perform a data transfer to transfer target data from a source to a destination. The direct memory access controller comprises an address generator having a set of iterators comprising a sample iterator, at least one frame iterator and at least one block iterator. The address generator is operable to generate a sequence of non-contiguous addresses by performing nested iteration of the set of iterators in accordance with an iterator hierarchy. The direct memory access controller is operable to perform the data transfer such that the destination data format differs from the source data format.

Abstract: A data processing apparatus and method of operation of such a data processing apparatus are disclosed. The data processing apparatus has a main processing unit operable to perform a plurality of data processing tasks, and a data engine for performing a number of those tasks on behalf of the main processing unit. At least one shared resource is allocatable to the data engine by the main processing unit for use by the data engine when performing data processing tasks on behalf of the main processing unit. The data engine comprises a data engine core for performing the tasks, and a data engine subsystem configurable by the main processing unit and arranged to manage communication between the data engine core and an allocated shared resource. The data engine core comprises a resource manager unit for acting as a master device with respect to the data engine subsystem in order to manage use of the allocated shared resource.

Abstract: A local FIFO memory 2 is provided within a local RAM memory 4 to provide access to source data values. A local controller 10 manages the asynchronous fetching of source data values to the local FIFO memory 2 and the optional writing back of these data values after processing to a source/sync memory 32. One or more local head pointers and one or more local tail pointers are used by the local memory controller 10 to manage storage within the local FIFO memory 2 which is configured as a circular buffer; The remaining space within the local RAM 4 may be used for further data and the partitioning between FIFO operation and further data storage is programmable such that the same memory storage 2 can be used for multiple purposes as required.

Abstract: A data processing system is provided comprising a main processor operable to perform a plurality of data processing tasks, a data engine having a data engine core operable to perform a number of said plurality of data processing tasks on behalf of said main processor and a data stream processing unit providing a data communication path between said main processing unit and said data engine core. The data stream processing unit has a control interface operable to receive from said data engine core at least one command and a data stream controller operable to receive at least one input data stream and to perform at least one operation on said at least one input data stream to generate at least one output data stream comprising a sequence of data elements. The data stream processing unit is responsive to said at least one command from said data engine core to control said data stream controller to perform said at least one operation.

Abstract: A multi-dimensional FFT is calculated upon 2n rows of 2m data values set out end-to-end in memory by traversing the data set as a whole using stride values and block sizes which halve upon each pass through the data. As the data values represent multi-dimensional data, there are one or more dimensional boundaries within the data and as these are crossed the coefficient values being applied by the complex butterfly calculation are adjusted to take account of the manipulation being performed. The linearity of the matrix calculations underlying the butterfly calculation means that the order in which these calculations are performed is not significant and accordingly multiple passes with appropriate coefficient changes can perform a multi-dimensional calculation even if the different components of the calculation in respect of each dimension arise upon different passes through the data set.

Abstract: Methods and apparatus are disclosed for automatically detecting when an operating channel needs to be changed in a wireless communication system. An alternate channel is selected by obtaining information about a plurality of available channels; assigning a score to each available channel; and selecting an alternate channel from the available channels based on the assigned score. The state of the selected alternate channel and the current channel are compared. A change to the selected alternate channel is initiated when one or more predefined criteria are satisfied.