Abstract: A host adapter connected between first and second buses, the first bus connected to a system memory or a central processing unit (CPU), the second bus connected to a storage apparatus. The host adapter includes first and second encryption/decryption processors and a first-in-first-out (FIFO) buffer. The first encryption/decryption processor is connected to the first type bus, and deciphers a data input through the first bus and enciphers a deciphered data by a second encryption/decryption processor using a first secret key. The second encryption/decryption processor is connected to the second bus, and enciphers the deciphered data from the first encryption/decryption processor and deciphers a data input through the second bus using a second secret key. The first-in-first-out (FIFO) buffer is connected between the first and second encryption/decryption processor and buffers the enciphered/deciphered data of the first and second encryption/decryption processors.