Abstract: An input/output (I/O) controller uses a single transceiver to service multiple I/O ports in a small computer system, such as an IBM PS/2 computer. Arbitration logic controls the access of the ports to the transceiver, and once the arbitration logic directs one of the ports to the transceiver, all other I/O devices are locked out until the transfer to or from the current I/O device is complete. Once the current transfer is complete, the arbitration logic then goes back to arbitrating, looking for the next I/O device that needs service. The associated circuitry to implement the arbitration and control logic is much smaller than the circuitry required for an additional transceiver, resulting in a lower system cost.

Abstract: An asynchronous latch circuit characterized by a pair of D-type flip-flops and a D-type latch. Data is clocked into a first flip-flop by a system clock signal and the output of the first flip-flop is clocked into a second flip-flop by an asynchronous latch enable signal. A comparator compares the outputs of the first and second flip-flops and develops an error signal if the two are not the same. The error signal forces the output of the latch to a known condition rather than letting the output be indeterminate. In an asynchronous latch register an error signal from any one of the asynchronous latch circuits will force all of the latch circuits in the register to a known condition to eliminate race condition errors.

Abstract: Apparatus for providing data available interrupts that have a variable threshold for reading data from a receiver FIFO, and for selecting the depth of a variable depth FIFO for use as either the receiver or transmitter FIFO of a UART. The interrupt circuit determines if the FIFO data level is at or exceeds a preselected threshold value, and if it doesn't, triggers the reduction of the threshold level after a preselected period of time if there has been no access of the FIFO. If the data available level is still less than the reduced threshold value, the threshold value is again reduced by a preselected value following each elapse of a second preselected pause between each resetting of the threshold level until either a data available interrupt occurs, the threshold level is dropped to zero, or the FIFO is accessed. Whenever the receiver FIFO is accessed, the threshold level is reset to the original preselected level.

Abstract: A combination keyboard and keyboard/mouse controller system is capable of use with different types of personal computers, using either a keyboard input alone or a keyboard/mouse combination. The controller is configured with a hardware transceiver in it, and includes interconnections between an accumulator and a microsequencer portion and a transceiver for effecting the transfer of data to and from the computer and the keyboard or keyboard/mouse combination. The configuration of the controller circuitry is such that logic gates and multiplex transmission gates are employed between various ones of the input terminals to which signals are applied, and output terminals to which signals are provided. These gates interconnect at least some of these terminals in different combinations in different modes of operation of the controller system, depending upon whether a computer uses a keyboard alone as a data input device or is operated with a combination of a keyboard and mouse.

Abstract: An asynchronous latch circuit characterized by a pair of D-type flip-flops and a D-type latch. Data is clocked into a first flip-flop by a system clock signal and the output of the first flip-flop is clocked into a second flip-flop by an asynchronous latch enable signal. A comparator compares the outputs of the first and second flip-flops and develops an error signal if the two are not the same. The error signal forces the output of the latch to a known condition rather than letting the output be indeterminate. In an asynchronous latch register an error signal from any one of the asynchronous latch circuits will force all of the latch circuits in the register to a known condition to eliminate race condition errors.

Abstract: A keycode translation system is disclosed in the form of a hardware system for providing translation between the keycode sent to the keyboard controller of a computer, such as a personal computer, and the code sent from the keyboard controller to the CPU of the computer for processing. A control ROM is used to select translated keycode signals from a keycode look-up table under the control of a program counter and keycode signals from the keyboard. These translated signals then are supplied through an accumulator to the CPU of the computer.