Abstract: An integrated circuit includes a pulse generator to provide an excitation pulse to an output terminal and a comparator to receive a signal in response to the excitation pulse and for comparing the signal to a threshold to produce a comparator output signal corresponding to oscillations in the signal. The integrated circuit further includes a counter to count pulses in the comparator output signal and a discriminator circuit to compare a count value of the counter to a damping threshold and for providing an output signal having a first value when the count value is equal to or exceeds the damping threshold and otherwise having a second value.

Abstract: An integrated circuit includes a pulse generator to provide an excitation pulse to an output terminal and a comparator to receive a signal in response to the excitation pulse and for comparing the signal to a threshold to produce a comparator output signal corresponding to oscillations in the signal. The integrated circuit further includes a counter to count pulses in the comparator output signal and a discriminator circuit to compare a count value of the counter to a damping threshold and for providing an output signal having a first value when the count value is equal to or exceeds the damping threshold and otherwise having a second value.

Abstract: A control bit vector storage is provided. The present control bit vector storage (preferably included within a functional unit) stores control bits indicative of a particular instruction. The control bits are divided into multiple control vectors, each vector indicative of one instruction operation. The control bits control dataflow elements within the functional unit to cause the instruction operation to be performed. Additionally, the present control bit vector storage allows complex instructions (or instructions which produce multiple results) to be divided into simpler operations. The hardware included within the functional unit may be reduced to that employed to perform the simpler operations. In one embodiment, the control bit vector storage comprises a plurality of vector storages. Each vector storage comprises a pair of individual vector storages and a shared vector storage. The shared vector storage stores control bits common to both control vectors.

Abstract: A control bit vector storage is provided. The present control bit vector storage (preferably included within a functional unit) stores control bits indicative of a particular instruction. The control bits are divided into multiple control vectors, each vector indicative of one instruction operation. The control bits control dataflow elements within the functional unit to cause the instruction operation to be performed. Additionally, the present control bit vector storage allows complex instructions (or instructions which produce multiple results) to be divided into simpler operations. The hardware included within the functional unit may be reduced to that employed to perform the simpler operations. In one embodiment, the control bit vector storage comprises a plurality of vector storages. Each vector storage comprises a pair of individual vector storages and a shared vector storage. The shared vector storage stores control bits common to both control vectors.

Abstract: A microprocessor including a pair of caches is provided. One of the pair of caches is accessed by stack-relative memory accesses from the decode stage of the instruction processing pipeline. The second of the pair of caches is accessed by memory accesses from the execute stage of the instruction processing pipeline. When a miss is detected in the first of the pair of caches, the stack-relative memory access which misses is conveyed to the execute stage of the instruction processing pipeline. When the stack-relative memory access accesses the second of the pair of caches, the cache line containing the access is transmitted to the first of the pair of caches for storage. The first of the pair of caches selects a victim line for replacement when the data is transferred from the second of the pair of caches. If the victim line has been modified while stored in the first cache, then the victim line is stored in a copyback buffer.

Abstract: A conditional latch circuit is provided wherein a first transmission gate is electrically coupled in series with a second transmission gate between an input node and an output node. The latch circuit is controlled by a conditional clock signal wherein a delay element is employed to cause both transmission gates to be simultaneously enabled upon an edge of the conditional clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input node is electrically coupled to the output node. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input node is decoupled from the output line by disabling the first transmission gate.

Abstract: An apparatus employs a flexible instruction categorization scheme which includes three categories: single dispatch, multiple dispatch, and microcode. Single dispatch instructions are performed in one functional unit. Conversely, multiple dispatch instructions are conveyed to multiple functional units, each of which perform a portion of the multiple dispatch instruction. A predefined fixed number of functional units are employed to execute a multiple dispatch instruction, allowing for additional instructions to be dispatched concurrently with the multiple dispatch instructions. In contrast to multiple dispatch instructions, microcode instructions may occupy a variable number of functional units and may dispatch instructions for a variable number of clock cycles. Additionally, multiple instruction operations may be performed in a given functional unit in response to an instruction. In one embodiment, up to two instruction operations may be performed in a functional unit.

Abstract: A microprocessor is provided including a pair of caches and a dependency checking structure for accesses between the pair of caches. One of the pair of caches is accessed from the decode stage of the instruction processing pipeline, while the other is accessed from the execute stage. The dependency checking structure monitors for memory dependencies between accesses to each of the pair of caches. Memory accesses may be performed earlier in the instruction processing pipeline than was previously achievable. Additionally, the dependency checking structure ensures that memory accesses receive the correct data by comparing accesses performed from each stage of the instruction processing pipeline to each other. In one embodiment, read and write dependency bits are stored by the cache which is accessed from the decode stage of the instruction processing pipeline. Decode stage accesses are recorded as a read or write by setting an associated dependency bit.

Abstract: A control bit vector storage is provided. The present control bit vector storage (preferably included within a functional unit) stores control bits indicative of a particular instruction. The control bits are divided into multiple control vectors, each vector indicative of one instruction operation. The control bits control dataflow elements within the functional unit to cause the instruction operation to be performed. Additionally, the present control bit vector storage allows complex instructions (or instructions which produce multiple results) to be divided into simpler operations. The hardware included within the functional unit may be reduced to that employed to perform the simpler operations. In one embodiment, the control bit vector storage comprises a plurality of vector storages. Each vector storage comprises a pair of individual vector storages and a shared vector storage. The shared vector storage stores control bits common to both control vectors.

Abstract: A pair of caches having a dependency checking structure for accesses between them is provided. One of the pair of caches is accessed from the decode stage of the instruction processing pipeline, while the other is accessed from the execute stage. The dependency checking structure monitors for memory dependencies between accesses to each of the pair of caches. Memory accesses may be performed earlier in the instruction processing pipeline than was previously achievable. Additionally, the dependency checking structure ensures that memory accesses receive the correct data by comparing accesses performed from each stage of the instruction processing pipeline to each other. In one embodiment, read and write dependency bits are stored by the cache which is accessed from the decode stage of the instruction processing pipeline. Decode stage accesses are recorded as a read or write by setting an associated dependency bit.

Abstract: A lookahead register value generator is provided which is configured to maintain lookahead values for registers with respect to instructions decoded in prior clock cycles. Each clock cycle, an instruction having one of these registers and an operand may receive a corresponding operand value generated using the values stored in these lookahead registers while the associated instruction is in the decode stage of the instruction processing pipeline. If the operand value is an address, the value may be used to fetch operand data residing at the address before the instruction arrives in the execute stage of the instruction processing pipeline. Additionally, the lookahead register value generator generates operand values for a second instruction which is dependent upon a concurrently decoded first instruction, thereby removing the dependency therebetween. Instructions for which the values are generated may execute concurrently, as opposed to serially executing.