Patents by Inventor Marty Lynn Pflum

Marty Lynn Pflum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10084469
    Abstract: A control system for an analog to digital converter (ADC) including a programmable configuration memory, a trigger selector, an input selector, and a conversion controller. The ADC is configurable for adjusting multiple operating parameters including speed and accuracy. The programmable configuration memory stores at least one configuration variable and an input value. The trigger selector enables at least one trigger input. The input selector selects from among multiple analog inputs according to the programmed input value. The conversion controller configures the ADC using the configuration variable, interfaces the input selector to provide an analog input to the ADC, and interfaces the trigger selector to prompt the ADC to perform a conversion process to provide a digital output sample in response to the enabled trigger input.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 25, 2018
    Assignee: SILICON LABORATORIES INC.
    Inventor: Marty Lynn Pflum
  • Patent number: 8402823
    Abstract: A metering system can include a pull up circuit to be selectively coupled between a voltage node and a metering line that communicates a signal indicative of status of a flow line through which a metered substance flows. An impedance of the pull up circuit is set to reduce power consumption based on a calibration, and the pull up circuit can be disabled between sampling of the signal to reduce power consumption.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: March 26, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Marty Lynn Pflum, Michael L. Duffy, Douglas S. Piasecki, Michael Keith Odland
  • Patent number: 8136409
    Abstract: An apparatus can include a first detector to receive a first signal from a first switch configured to open and close based on position of a metering wheel associated with a flow line. The apparatus can further include a first counter to count within a first range based on a change in a state of the first signal. Using this information, the apparatus can determine usage and direction of, e.g., a fluid or liquid flowing along the flow line.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 20, 2012
    Assignee: Silicon Laboratories Inc.
    Inventor: Marty Lynn Pflum
  • Publication number: 20110291678
    Abstract: A metering system can include a pull up circuit to be selectively coupled between a voltage node and a metering line that communicates a signal indicative of status of a flow line through which a metered substance flows. An impedance of the pull up circuit is set to reduce power consumption based on a calibration, and the pull up circuit can be disabled between sampling of the signal to reduce power consumption.
    Type: Application
    Filed: March 31, 2011
    Publication date: December 1, 2011
    Inventors: Marty Lynn Pflum, Michael L. Duffy, Douglas S. Piasecki, Michael Keith Odland
  • Publication number: 20110290036
    Abstract: An apparatus can include a first detector to receive a first signal from a first switch configured to open and close based on position of a metering wheel associated with a flow line. The apparatus can further include a first counter to count within a first range based on a change in a state of the first signal. Using this information, the apparatus can determine usage and direction of, e.g., a fluid or liquid flowing along the flow line.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Inventor: Marty Lynn Pflum
  • Patent number: 8023557
    Abstract: A method is disclosed for controlling the operation of a low power radio platform that realizes the physical layer (PHY) with a software portion and an analog front end, the analog front end disposed between the DSP and an antenna, and realizes the MAC layer with a microcontroller unit (MCU). The DSP, analog front end and MCU are maintained in a low power mode of operation when not in data communication. When data communication is initiated, a hardware controller controls at least one hardware interface disposed between the DSP and the analog front end to initiate multiple time based tasks to transfer data to and from a buffer. During the execution of these tasks, the controller causes a task in the DSP to be initiated for processing of data in the buffers and, upon completion of at least one of the tasks, notifying the MCU of such. The controller controls the hardware interface to terminate operation when predetermined time based events have occurred.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: September 20, 2011
    Assignee: Silicon Laboratories Inc.
    Inventors: Nicolas Constantinidis, Guillaume Crinon, Alexandre Rouxel, Alan Westwick, Gary Franzosa, Didier Gallais, Marty Lynn Pflum
  • Publication number: 20090168939
    Abstract: A method is disclosed for controlling the operation of a low power radio platform that realizes the physical layer (PHY) with a software portion and an analog front end, the analog front end disposed between the DSP and an antenna, and realizes the MAC layer with a microcontroller unit (MCU). The DSP, analog front end and MCU are maintained in a low power mode of operation when not in data communication. When data communication is initiated, a hardware controller controls at least one hardware interface disposed between the DSP and the analog front end to initiate multiple time based tasks to transfer data to and from a buffer. During the execution of these tasks, the controller causes a task in the DSP to be initiated for processing of data in the buffers and, upon completion of at least one of the tasks, notifying the MCU of such. The controller controls the hardware interface to terminate operation when predetermined time based events have occurred.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: SILICON LABORATORIES INC.
    Inventors: NICOLAS CONSTANTINIDIS, GUILLAUME CRINON, ALEXANDRE ROUXEL, ALAN WESTWICK, GARY FRANZOSA, Didier Gallais, Marty Lynn Pflum
  • Patent number: 7296085
    Abstract: Handshaking is performed between a first host system and a second host system. First handshaking is performed between a host module within the first host system and a first transceiver within the first host system. The first handshaking includes passing from the first transceiver to the host module dummy information about the second host system. Second handshaking is performed between a second transceiver within the second host system and the first transceiver. The second handshaking includes obtaining, by the first transceiver from the second transceiver, first information about the second host system. Handshaking between the host module and the first transceiver is restarted. This includes passing from the first transceiver to the host module the first information about the second host system. The first information replaces the dummy information passed from the first transceiver to the host module during the first handshaking.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: November 13, 2007
    Assignee: Avago Technologies Fiber IP (Singapore) Pte Ltd
    Inventors: Andy Engel, Janet L. Yun, Allan Liu, Marty Lynn Pflum, Robert Thomas Grisamore
  • Publication number: 20040019694
    Abstract: Handshaking is performed between a first host system and a second host system. First handshaking is performed between a host module within the first host system and a first transceiver within the first host system. The first handshaking includes passing from the first transceiver to the host module dummy information about the second host system. Second handshaking is performed between a second transceiver within the second host system and the first transceiver. The second handshaking includes obtaining, by the first transceiver from the second transceiver, first information about the second host system. Handshaking between the host module and the first transceiver is restarted. This includes passing from the first transceiver to the host module the first information about the second host system. The first information replaces the dummy information passed from the first transceiver to the host module during the first handshaking.
    Type: Application
    Filed: July 26, 2002
    Publication date: January 29, 2004
    Inventors: Andy Engel, Janet L. Yun, Allan Liu, Marty Lynn Pflum, Robert Thomas Grisamore
  • Patent number: 6604206
    Abstract: Reduced GMII with internal timing compensation A data interface between first and second integrated circuits. An internal clock signal is generated internal to the first integrated circuit and operates in a first frequency. A data generator is provided for generating data from at least one edge of the internal clock for transmission to the second integrated circuit. a first delay block internal to the first integrated circuit delays the internal clock for a predetermined duration of time less than one-half clock cycle of said internal clock to provide a first delayed clock. The second integrated circuit is then operable to receive the transmitted first delayed clock and utilize the transmitted first delayed clock to sample the received data generated by the data generator.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: August 5, 2003
    Assignee: Cicada Semiconductor Corporation
    Inventors: Mandeep Singh Chadha, Marty Lynn Pflum, Nicholas van Bavel
  • Publication number: 20020184550
    Abstract: Reduced GMII with internal timing compensation A data interface between first and second integrated circuits. An internal clock signal is generated internal to the first integrated circuit and operates in a first frequency. A data generator is provided for generating data from at least one edge of the internal clock for transmission to the second integrated circuit. a first delay block internal to the first integrated circuit delays the internal clock for a predetermined duration of time less than one-half clock cycle of said internal clock to provide a first delayed clock. The second integrated circuit is then operable to receive the transmitted first delayed clock and utilize the transmitted first delayed clock to sample the received data generated by the data generator.
    Type: Application
    Filed: May 30, 2001
    Publication date: December 5, 2002
    Inventors: Mandeep Singh Chadha, Marty Lynn Pflum, Nicholas van Bavel
  • Patent number: 6170825
    Abstract: Dual hexagon shaped playing fields composed of smaller hexagons of two different colors vertically separated for visibility with each player starting with the same number of three different shaped playing pieces with each piece being limited differently in movement and capture capability with such limitations designed to make each piece of approximately the same worth to a player in his effort to capture the opponent's pieces and conscript the captured pieces for his use.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: January 9, 2001
    Inventor: Marty Lynn Pflum