Abstract: A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.

Abstract: A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a predicted target address, determining the predicted target address using the portion of the predicted target address stored in the first entry and a portion of a branch address of a fetched branch instruction for a fetched branch instruction of a first type, and determining the predicted target address using the portion of the predicted target address stored in the first entry and the portion of the predicted target address stored in the second entry for a fetched branch instruction of a second type.

Abstract: A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an instruction being speculatively executed a first time; and provides a second instance of the branch prediction value associated with the instruction being speculatively executed a second rime. The first instance of the branch prediction value may be subsequently revised after the instruction associated with the first instance of the branch prediction value is retired. Information regarding whether that branch instruction was accurately predicted may then be used to update the branch prediction table and the second instance of the branch prediction value.

Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Abstract: A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition precedent and a received branch instruction. After executing each branch instruction, the branch unit predicts whether the condition precedent will be met the next time it encounters the same branch instruction. If the predicted value of the condition precedent would cause the branch to be taken, then the branch unit adds the fetch address-target address pair corresponding to the branch instruction to the BTAC. If the predicted value of the condition precedent would cause the branch to be not taken, then the branch unit deletes the fetch address-target address pair corresponding to the branch instruction from the BTAC.

Abstract: A data processor (10) has a branch target address cache (48) for storing the target addresses of a number of recently taken branch instructions. Normally, each fetch address is compared to the contents of the branch target address cache. If a hit occurs, then the data processor branches to the cached target address. The data processor also has a dispatch unit (60) that invalidates the data stored in the branch target address cache if and when it determines that the branch target address cache "hit" on an instruction that was not a branch instruction at all, a "phantom branch." The data processor thereby automatically invalidates its branch target address cache data after a context switch.

Abstract: A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units.

Abstract: The disclosed data processor (10) dispatches load/store multiple and load/store string instructions to a load/store unit (28) as a sequence of simple load or store instructions. The sequencer unit (18) assigns an entry of a rename buffer (34) to which the load/store unit writes back the data of each simple load instruction. This strategy facilitates early data forwarding for subsequent instructions. Conversely, the sequencer unit supplies a rename buffer tag to the load/store unit if it is not able to supply the operands of a simple store instruction.

Abstract: A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units.

Abstract: A data processor (10) has an execution unit (18, 20) for generating the address of each requested data double-word. The data processor fetches the entire memory line, four double-words of data, containing the requested double-word when the requested double-word is not found in the data processor's memory cache. The data processor ultimately stores the requested data in the memory cache (40) when returned from an external memory system. The data processor also has forwarding circuitry (48, 50) for forwarding previously requested double-words directly to the execution unit under certain circumstances. The forwarding circuitry will forward a requested double-word if the data processor has not crossed a memory line boundary since the last memory cache miss and if the two least significant bits of the requested and received double-words logically match.

Abstract: A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. Each pair also includes an offset tag identifying which one of a plurality of instructions indexed by the fetch address generated the entry. A branch unit (20) generates an execution address that depends upon one of the plurality of instructions. After executing each instruction, the branch unit may delete an entry from the BTAC if the instruction's execution address differs from the target address and if the instruction is the same instruction which generated the BTAC entry initially.

Abstract: A processing system and method of operation are provided, In response to a branch instruction, a first instruction is processed so that a storage location is associated with the first instruction prior to execution of the branch instruction. In response to execution of the branch instruction, a second instruction is processed independent of information previously stored in the storage location so that the storage location is associated with the second instruction prior to completion of the branch instruction.

Abstract: A data processor has a plurality of execution units (12), a rename buffer (14) coupled to at least one of the execution units and a plurality of architectural registers (16) coupled to at least one execution unit and to the rename buffer. The rename buffer periodically receives and stores the result and periodically receives requests for the operand. Each received result and operand is associated with an architectural register. The rename buffer periodically forwards one of a set of received results to an execution unit. Each received result of the set is associated with the same architectural register. The rename buffer is operable to determine which entry is the most recently allocated among several that will update the same architectural register. This ability to both manage results destined for the same architectural register and to forward only the appropriate value increases data processor throughput and reduces instruction stalls.

Abstract: A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.

Abstract: A circuit for use in conjunction with a multiplier receives a portion of completed product bits and a portion of sum and carry bits which, when accumulated, provide a complete output product operand. The circuit is adaptable for use with input operands having single or double precision data formats. The accumulation time required depends upon which data format mode the circuit is operating in.

Abstract: In a data processor having an integer arithmetic unit, the carry-in control logic, carry-out control logic, and the overflow control logic of the arithmetic unit are adapted to be directly controlled by respective carry-in enable, carry-out enable, and overflow enable fields of the integer arithmetic instructions during the execution thereof.