Abstract: A sensor system and a method of operating a sensor system including a plurality of sensors tracking a moving object in an area having known bounding surfaces. The apparatus and method calculate a time-specific position of the object based on data and sensor parameters from at least two of the plurality of sensors and determine errors between the calculated time-specific positions calculated. The method and apparatus calculate a minimum system error attributable to the at least two sensors by constraining at least one dimension in the data of the sensor used in the calculated time-specific position of the object associated with the sensor, the constraining based on an object/surface interaction, the minimum system error calculated by solving for modified sensor parameters for each sensor.

Abstract: A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

Abstract: A CCD image sensor has a plurality of elements, each such sensing element includes a doped semiconductor substrate, an insulator layer over the semiconductor substrate, and an electrode on the insulator layer which when potential is applied to the electrode creates a well in the bulk of the substrate which collects charge as a result of a photoelectric process. The insulator layer has a thin portion selected so as to allow excess charge collected in the channel to tunnel through the thin region to the electrode and thereby prevent blooming.

Abstract: An adaptive analog processor incorporating a analog shift register having a plurality of taps, multipliers at each tap for multiplying the tap value times a weight value, a first adder for summing the output of the multipliers, a second adder for subtracting the output of the adder from a second analog signal, means for incrementing the weights in response to the magnitude and polarity of the error signal and the polarity of the data signal. The invention overcomes the problem of building monolithic multitap adaptive filters utilizing the clipped-data least mean square error algorithm.

Abstract: A charge control circuit for bidirectionally transferring metered amounts of charge, selectively, through a transfer channel of a four gate electrode charge coupled device (CCD) is disclosed. The bidirectional charge control circuit is used primarily to increment and decrement metered amounts of charge respectively to and from a charge storage medium. More specifically, five electrical signals are generated to have varying potentials in accordance with predetermined time sequences. These signals are applied to the four gate electrode CCD in a selected one of two states to either increment or decrement a metered amount of charge therethrough to or from the charge storage medium respectively, in a predetermined number of five segments. One of the generated signals governs the metering of charge for each increment or decrement operation.

Abstract: An imaging system comprising a multi-channel matrix array of CCD devices wherein a plurality of sensor cells (pixels) in each channel are subdivided and operated in discrete intercoupled groups or subarrays with a readout CCD shift register terminating each end of the channels. Clock voltages are applied to the subarrays and are manipulated to selectively cause charge signal flow in each subarray in either direction independent of the other subarrays. More particularly, the array is divided into six independent subarrays, three on each side of the array, such that each channel common to three subarrays is divided into three sections of three sensor cells each. By selective application of four phase clock voltages, either one, two or all three of the sections cause charge signal flow in one direction, while the remainder cause charge signal flow in the opposite direction.

Abstract: Apparatus for forming one or more sonar beams in response to acoustic energy received by a transducer array. To minimize volume utilization, a plurality of CCD's are formed on an integrated circuit chip with the CCD's being of progressively smaller length. Half of the CCD array is folded over to match the other half so that each CCD has an opposing CCD with both CCD's propagating a signal toward a common output diode. By providing one integrated circuit chip for each desired beam with appropriately different clocking frequencies multiple beams may be formed, and with the provision of a variable clocking frequency, one or more beams may be steered.Transversal filter operations may also be performed by the apparatus.

Abstract: An analog multiplier for multiplying the signals derived from a charge coupled device (CCD) tap includes a balanced multiplier of a first conductivity-type and a buffer of a second conductivity-type coupled between the CCD tap and the balanced multiplier. The multiplier includes first and second transistors, the drains of which are coupled together to form an input. The buffer includes a load transistor coupled to the output of an amplifying transistor. Means are included for coupling the output of the amplifier transistor and the multiplier input.

Abstract: A stabilized charge injector for charge coupled devices (CCD) includes a diffusion and two or more gate structures in a CCD channel wherein the diffusion alternately acts as a source and drain of the minority-type signal carriers. D.C. signals are applied to the gates immediately adjacent the diffusion and the next successive adjacent gate to provide a charge injection which is proportional to the difference between the signal voltage applied to the one of the two gates and a DC reference voltage applied to the other thereof. Low noise performance is achieved through utilization of a quasi-static operation in which neither of the aforementioned gates adjacent the diffusion is pulsed. Moreover, the use of a gate injector presents at the input, a true capacitance defined as a function of the gate oxide layer. Hence, the value of capacitance is constant and independent of the signal voltage applied.

Abstract: An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions.

Abstract: An N-channel MOS transistor wherein two layers of different dielectric materials (e.g., silicon dioxide and silicon nitride) are used in conjunction with a P-doped silicon gate to permit the use of a higher resistivity P-type substrate. This enables a higher junction breakdown voltage and a higher threshold voltage without a reverse bias on the substrate due to an increase in the work function difference between the gate and substrate. Because of the lower concentration (i.e., higher resistivity) of the substrate, high frequency response is increased due to lower drain-source capacitance.

Abstract: In a charge transfer device (CTD), such as a charge coupled device (CCD), a gate electrode employed for sensing of the charge packet being transferred, or coupled through the device is clocked during one phase of the four-phase clocking and is permitted to float, i.e., be isolated, during a sensing phase of the four-phase clocking. Since the sensor is a gate electrode rather than a diffusion, it presents no obstruction to the propagation of charge down the channel. Since sensing occurs while the electrode is floating, the sensing or readout function does not have any detrimental effect on the propagation of charge down the channel, i.e., it affords a truly non-destructive readout. During a clocking phase in which charge is isolated under a different gate electrode, an attractive voltage clock pulse is applied to the sensor electrode, rendering it attractive.

Abstract: Extended correlated double sampling (ECDS) for charge transfer devices (CTD) corrects for errors arising in components of the CTD system from the input to the output thereof. Sources of error include bias variations and non-uniformity of thresholds and leakage currents. While applicable to any type of CTD system, for a TDI (time delay integration) application, precise error correction is achieved. Alternate signal level samples and reference level samples, the latter preferably AC zero, are propagated down the CTD channel as a related pair. At the CTD output, the signal and reference level samples of each pair are differenced, thereby correcting the resultant output signal for the noted types of errors. ECDS is compatible with CDS as taught in U.S. Pat. No. 3,781,574 and the two may be used jointly.

Abstract: A programmable analog transversal filter is disclosed for processing analog signals and comprising a charge-coupled device (CCD) for receiving a series of discrete analog signals to be delayed by increasing periods and applied to the outputs of the CCD, and a plurality of MNOS memory devices coupled to the taps of the CCD and programmed so that the output of a CCD tap is multiplied by a particular factor. In turn, the outputs of the MNOS memory devices are summed to provide an output signal ##EQU1## where W.sub.k is the weighting factor associated the k.sup.th MNOS memory device. The weighting factors are set into the system by varying the threshold voltage of the corresponding MNOS device.

Abstract: A coherent sampled CMOS readout circuit and signal processor coupled to a CCD shift register operated by a two-phase minority carrier transfer clock system. The invention comprises a multiplex MIS switch, a reverse biased collection diode, an N channel MOSFET reset switch, a P channel MOSFET electrometer amplifier, and a sample and hold circuit, the configuration having four distinct operational timing subintervals within a clock period wherein the charge is shifted from one shift register bit to another and finally to the output bit. This removes the Nyquist noise associated with the reset switch, suppresses switching transients and 1/f surface noise to thereby improve the signal to noise ratio, i.e., dynamic range, for a CCD array and readout system.