Abstract: In a data processing system, there is included a central processing unit (CPU) and a main memory for storing computer words, the CPU including a cache unit. In operation, the CPU requests that a computer word be fetched, the computer word to be fetched being identified by a real address location corresponding to a location where the predetermined computer word is stored in main memory. The CPU request to fetch the computer word is coupled through the cache unit such that the cache unit determines whether the computer word is stored within the cache unit. The cache unit comprises a cache for storing predetermined ones of the compter words. A directory is included for storing partial real address information to a corresponding computer word stored in the cache. A detecting element, operatively connected to the cache and to the directory, determines when a hit occurs without any errors.

Abstract: In a cache memory unit including a cache directory identifying signal groups stored in an associated cache storage unit, apparatus and method are disclosed for searching the cache directory during a second portion of the cache memory cycle when the cache directory is not needed for normal operation, to determine if an invalid signal group is stored in the associated cache storage. When an invalid signal is found in the cache storage, this signal group is rendered unavailable to the data processing unit during the present cache memory cycle without interrupting the normal cache memory operation during succeeding cache memory cycles.

Abstract: In a stack for use in a data processing system memory controller, information which includes data, instructions and/or commands generated by a requesting unit requesting access to memory are accepted and temporarily stored in the stack if such memory is unavailable. The newest information from any requesting unit that must be temporarily stored is stored in the lowest unoccupied level of the stack. Associated with each stack level is a busy flip-flop which is set when the information is stored in its associated stack level. The busy flip-flop is reset when the information is given access to the memory. The level busy flip-flops are monitored to detect when the stack is full thus indicating that further requests be inhibited. By monitoring the number of levels in the stack that are filled at various times, a measure of throughput can be achieved in order to determine whether the stack should be enlarged or made smaller.

Abstract: This relates to an apparatus for assigning priority to information temporarily stored in memory controller stack. Associated with each level of the stack is a counter which measures the length of time the information has been stored. A plurality of comparators and associated control logic determines the stack level which contains information which has been stored the longest. If the destination memory associated with the contents of this level becomes available, this level is given priority with respect to transmission to its destination memory.

Abstract: Initializing apparatus for a dynamic memory causes data to be written into a different cell of each array of the memory during each refresh cycle until all the memory cells of the arrays have data written into them. The memory initializing apparatus then ceases causing data to be written into the array during subsequent refresh cycles.