Abstract: Aspects of this disclosure relate to an amplifier with at least two chopper amplifier channels in parallel between a shared input and differential nodes. The amplifier can multiplex outputs of the chopper amplifier channels to provide the output of one or more chopper amplifier channels to the differential nodes at a time. In certain embodiments, this can mask dynamic settling errors.

Abstract: Aspects of this disclosure relate to an amplifier with at least two chopper amplifier channels in parallel between a shared input and differential nodes. The amplifier can multiplex outputs of the chopper amplifier channels to provide the output of one or more chopper amplifier channels to the differential nodes at a time. In certain embodiments, this can mask dynamic settling errors.

Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.