Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.

Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.

Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.

Abstract: A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer.

Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.

Abstract: A semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution layer has a first surface and a second surface opposite to each other. The chip is disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer. The interconnecting bumps are disposed over the first surface and electrically connected to the redistribution layer. The encapsulant is disposed over the first surface of the redistribution layer, and the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.

Abstract: A semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution layer has a first surface and a second surface opposite to each other. The chip is disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer. The interconnecting bumps are disposed over the first surface and electrically connected to the redistribution layer. The encapsulant is disposed over the first surface of the redistribution layer, and the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.

Abstract: A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: A structure is formed in an integrated circuit to provide for the coupling of elements in the integrated circuit. The structure extends from a conductive surface through a channel extending above the conductive surface. The structure includes a layer of a refractory metal, a layer of a metal nitride, and a layer of a metal. The layer of the refractory metal is deposited on the conductive surface and inner walls of the channel. The layer of the metal nitride is formed on the layer of the refractory metal. The layer of the metal nitride has a thickness extending from the layer of the refractory metal of less than 130 Å. The layer of the metal is deposited on the layer of the metal nitride.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: A layer of material is formed on a substrate in a partially formed integrated circuit on a wafer. The substrate undergoes a plasma annealing, during which the substrate is bombarded with ions. The plasma annealing may be performed by exposing the substrate to plasma that is generated from a nitrogen containing gas which is infused with energy. After the substrate is plasma annealed, a layer of a refractory metal nitride is deposited on the substrate. The layer of refractory metal nitride is then bombarded with a first set of ions. The bombardment of the refractory metal by the first set of ions may be achieved by performing a plasma annealing. The refractory metal nitride may be further bombarded by a second set of ions.