Patents by Inventor Marvin Lo

Marvin Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8672231
    Abstract: A system for manufacturing an integrated circuit system having a substrate with a integrated circuit device. A first pad is formed on the substrate and connected to the integrated circuit device. A first dielectric layer is formed over the substrate and the first pad, with the first dielectric layer having an opening provided therein exposing the first pad. An upper redistribution layer is formed over the first dielectric layer. A portion of the upper redistribution layer is formed into an antenna with the antenna connected to the first pad. A second dielectric layer is formed over the first dielectric layer and over the antenna.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: David Yeo, Victor Tan, Marvin Lo, Kai Keong Cheong, Stanley Bay, Anthony Yong
  • Publication number: 20090014543
    Abstract: A system for manufacturing an integrated circuit system having a substrate with a integrated circuit device. A first pad is formed on the substrate and connected to the integrated circuit device. A first dielectric layer is formed over the substrate and the first pad, with the first dielectric layer having an opening provided therein exposing the first pad. An upper redistribution layer is formed over the first dielectric layer. A portion of the upper redistribution layer is formed into an antenna with the antenna connected to the first pad. A second dielectric layer is formed over the first dielectric layer and over the antenna.
    Type: Application
    Filed: September 22, 2008
    Publication date: January 15, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: David Yeo, Victor Tan, Marvin Lo, Kai Keong Cheong, Stanley Bay, Anthony Yong
  • Patent number: 7444735
    Abstract: A system for manufacturing an integrated circuit system having a substrate with a integrated circuit device. A first pad is formed on the substrate and connected to the integrated circuit device. A first dielectric layer is formed over the substrate and the first pad, with the first dielectric layer having an opening provided therein exposing the first pad. An upper redistribution layer is formed over the first dielectric layer. A portion of the upper redistribution layer is formed into an antenna with the antenna connected to the first pad. A second dielectric layer is formed over the first dielectric layer and over the antenna.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: November 4, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: David Yeo, Victor Tan, Marvin Lo, Kai Keong Cheong, Stanley Bay, Anthony Yong
  • Patent number: 7443040
    Abstract: A resulting solder bump structure comprising the following steps. A structure having a metal bond pad formed thereover is provided. A patterned cover layer is formed over the structure. The patterned cover layer including an opening exposing a portion of the metal bond pad. The patterned cover layer opening including side walls. A metal cap layer is formed over at least the exposed portion of the metal bond pad and the patterned cover layer side walls. A solder bump is formed over the metal cap layer.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: October 28, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Marvin Lo
  • Publication number: 20060214310
    Abstract: A resulting solder bump structure comprising the following steps. A structure having a metal bond pad formed thereover is provided. A patterned cover layer is formed over the structure. The patterned cover layer including an opening exposing a portion of the metal bond pad. The patterned cover layer opening including side walls. A metal cap layer is formed over at least the exposed portion of the metal bond pad and the patterned cover layer side walls. A solder bump is formed over the metal cap layer.
    Type: Application
    Filed: June 6, 2006
    Publication date: September 28, 2006
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventor: Marvin Lo
  • Patent number: 7081372
    Abstract: A method of forming a solder bump (and the resulting solder bump structure), comprising the following steps. A structure having a metal bond pad formed thereover is provided. A patterned cover layer is formed over the structure. The patterned cover layer including an opening exposing a portion of the metal bond pad. The patterned cover layer opening including side walls. A metal cap layer is formed over at least the exposed portion of the metal bond pad and the patterned cover layer side walls. A solder bump is formed over the metal cap layer.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: July 25, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Marvin Lo
  • Publication number: 20050276028
    Abstract: A system for manufacturing an integrated circuit system having a substrate with a integrated circuit device. A first pad is formed on the substrate and connected to the integrated circuit device. A first dielectric layer is formed over the substrate and the first pad, with the first dielectric layer having an opening provided therein exposing the first pad. An upper redistribution layer is formed over the first dielectric layer. A portion of the upper redistribution layer is formed into an antenna with the antenna connected to the first pad. A second dielectric layer is formed over the first dielectric layer and over the antenna.
    Type: Application
    Filed: June 2, 2005
    Publication date: December 15, 2005
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: David Yeo, Victor Tan, Marvin Lo, Kai Keong Cheong, Stanley Bay, Anthony Yong
  • Publication number: 20050009289
    Abstract: A method of forming a solder bump (and the resulting solder bump structure), comprising the following steps. A structure having a metal bond pad formed thereover is provided. A patterned cover layer is formed over the structure. The patterned cover layer including an opening exposing a portion of the metal bond pad. The patterned cover layer opening including side walls. A metal cap layer is formed over at least the exposed portion of the metal bond pad and the patterned cover layer side walls. A solder bump is formed over the metal cap layer.
    Type: Application
    Filed: July 9, 2003
    Publication date: January 13, 2005
    Inventor: Marvin Lo