Patents by Inventor Marvin R. DeForest
Marvin R. DeForest has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9305142Abstract: Embodiments described herein include systems and methods for managing security of a storage subsystem. Certain of these embodiments involve the use of a buffer protection module configured to intelligently police requests for access to the subsystem buffer memory.Type: GrantFiled: December 19, 2011Date of Patent: April 5, 2016Assignee: Western Digital Technologies, Inc.Inventors: Danny O. Ybarra, Marvin R. Deforest, Alan T. Meyer
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Patent number: 9274978Abstract: Systems and methods for compression, formatting, and migration of data for data storage systems are disclosed. In some embodiments, data repacking can be used in any situation where embedded metadata needs to be accessed, such as during data migration, and where the underlying data is encrypted. In some embodiments, performance is increased because encrypted data is repacked without first performing decryption. In addition, data may also be compressed and repacking can be performed without performing decompression. Advantageously, there is no need to retrieve or wait for the availability of encryption key (or keys) or expand resources in decrypting (and decompressing) data before repacking it and encrypting repacked data. Available capacity for storing user data, reliability, and performance of the data storage system can be increased.Type: GrantFiled: August 26, 2013Date of Patent: March 1, 2016Assignee: Western Digital Technologies, Inc.Inventors: Marvin R. DeForest, Robert L. Horn
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Publication number: 20140365785Abstract: Systems and methods for compression, formatting, and migration of data for data storage systems are disclosed. In some embodiments, data repacking can be used in any situation where embedded metadata needs to be accessed, such as during data migration, and where the underlying data is encrypted. In some embodiments, performance is increased because encrypted data is repacked without first performing decryption. In addition, data may also be compressed and repacking can be performed without performing decompression. Advantageously, there is no need to retrieve or wait for the availability of encryption key (or keys) or expand resources in decrypting (and decompressing) data before repacking it and encrypting repacked data. Available capacity for storing user data, reliability, and performance of the data storage system can be increased.Type: ApplicationFiled: August 26, 2013Publication date: December 11, 2014Applicant: Western Digital Technologies, Inc.Inventors: MARVIN R. DEFOREST, ROBERT L. HORN
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Patent number: 8423722Abstract: Solid State Drives (SSD) can yield very high performance if it is designed properly. A SSD typically includes both a front end that interfaces with the host and a back end that interfaces with the flash media. Typically SSDs include flash media that is designed with a high degree of parallelism that can support a very high bandwidth on input/output (I/O). A SSD front end designed according to a traditional hard disk drive (HDD) model will not be able to take advantage of the high performance offered by the typical flash media. Embodiments of the invention provide improved management of multiple I/O threads that take advantage of the high performing and concurrent nature of the back end media, so the resulting storage system can achieve a very high performance.Type: GrantFiled: August 26, 2011Date of Patent: April 16, 2013Assignee: Western Digital Technologies, Inc.Inventors: Marvin R. Deforest, Matthew Call, Mei-Man L. Syu
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Data storage device comprising host interface state machine blocking on target logical block address
Patent number: 8380922Abstract: A data storage device is disclosed wherein a host interface state machine receives an access command from a host, the access command identifying a plurality of logical block addresses (LBAs). A host interface processor generates at least one control structure executed by the host interface state machine in connection with servicing the access command. The host interface processor directs a master processor to execute the access command, and the master processor updates a LBA register in connection with executing the access command. The host interface state machine executes the control structure to compare a target LBA to the LBA register and communicates with the host in response to the comparison.Type: GrantFiled: June 25, 2010Date of Patent: February 19, 2013Assignee: Western Digital Technologies, Inc.Inventors: Marvin R. DeForest, Christopher J. Reed -
Patent number: 7587656Abstract: A device can receive information to be stored in a first part of a first portion of a block, read previously-stored information from a second part, and store the specified information in the first part and simulate storage of the previously-stored information in the second part while generating error detection information which is then stored in a second portion of the block. The device can read a specified subset of sections in a block, use part of each section to detect and/or correct an error in another part thereof, while avoiding reading the error detection information unless a section in the subset has an uncorrected error. Detected errors are corrected with successive correction stages, while maintaining for each section being processed in the stages a count of the number of other sections which are thereafter read in succession without error.Type: GrantFiled: May 29, 2003Date of Patent: September 8, 2009Assignee: Iomega CorporationInventors: Troy D. Larsen, Martin L. Culley, Marvin R. DeForest
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Publication number: 20040243912Abstract: A device can receive information to be stored in a first part of a first portion of a block, read previously-stored information from a second part, and store the specified information in the first part and simulate storage of the previously-stored information in the second part while generating error detection information which is then stored in a second portion of the block. The device can read a specified subset of sections in a block, use part of each section to detect and/or correct an error in another part thereof, while avoiding reading the error detection information unless a section in the subset has an uncorrected error. Detected errors are corrected with successive correction stages, while maintaining for each section being processed in the stages a count of the number of other sections which are thereafter read in succession without error.Type: ApplicationFiled: May 29, 2003Publication date: December 2, 2004Inventors: Troy D. Larsen, Martin L. Culley, Marvin R. DeForest
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Patent number: 6779067Abstract: An information storage device (10) includes a cartridge (14) removably inserted into a cradle (13) that has a drive module (18) releasably coupled to an interface module (17). A drive electronics circuit (71) in the drive module is coupled to a hard disk drive mechanism (56) in the cartridge, and is coupled through a bus switch (131) and a bus (122) to a bridge circuit (111) in the interface module. An auxiliary circuit (76) in the drive module is coupled to the bus, is controlled by the bridge circuit, operates the bus switch, and handles considerations relating to removability of the cartridge. The interface module is one of several interchangable interface modules which each have a different bridge circuit to interface the bus to a respective different communication protocol.Type: GrantFiled: May 14, 2001Date of Patent: August 17, 2004Assignee: Iomega CorporationInventors: Todd R. Shelton, Theodore J. Smith, Marvin R. DeForest, Kelly D. Wright, Mark L. Reimann, Hiromichi Oribe, Jeffery D. Penman
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Patent number: 6624979Abstract: An information storage device (10, 510, 610, 710) includes a cradle (12, 512, 612, 712) which can removably receive a cartridge (11, 411, 511, 611, 711). The cartridge has a sealed housing (59) which contains a rotatably supported disk (91, 326-327), and a pivotal actuator arm (101) that supports a magnetic head (107, 331-334) for movement adjacent the disk. When the cartridge is removed from the cradle, the head is moved to a parked position with respect to the disk, in which a magnetically permeable part (116) on the actuator arm is in close proximity to a magnetic arrangement (141) disposed within the housing. The magnetic arrangement exerts a strong magnetic force that resists movement of the arm and head away from the parked position. The cradle has a shunt (142) which, when the cartridge is removably inserted, interacts with the magnetic field through a wall of the sealed housing, in a manner which reduces the effective magnetic force that tends to retain the arm and head in the parked position.Type: GrantFiled: June 9, 2000Date of Patent: September 23, 2003Assignee: Iomega CorporationInventors: Thomas A. Wilke, Marvin R. DeForest, Dennis D. Ogden
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Publication number: 20020169911Abstract: An information storage device (10) includes a cartridge (14) removably inserted into a cradle (13) that has a drive module (18) releasably coupled to an interface module (17). A drive electronics circuit (71) in the drive module is coupled to a hard disk drive mechanism (56) in the cartridge, and is coupled through a bus switch (131) and a bus (122) to a bridge circuit (111) in the interface module. An auxiliary circuit (76) in the drive module is coupled to the bus, is controlled by the bridge circuit, operates the bus switch, and handles considerations relating to removability of the cartridge. The interface module is one of several interchangable interface modules which each have a different bridge circuit to interface the bus to a respective different communication protocol.Type: ApplicationFiled: May 14, 2001Publication date: November 14, 2002Inventors: Todd R. Shelton, Theodore J. Smith, Marvin R. DeForest, Kelly D. Wright, Mark L. Reimann, Hiromichi Oribe, Jeffery D. Penman
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Patent number: 6327105Abstract: A highly reliable, low overhead method for determining a position of a magnetic storage medium that is divided into a plurality of servo sections is provided. The inventive method includes defining a predetermined bit pattern that corresponds to a known position of the magnetic storage medium. A positional index bit is associated with each servo section such that a known bit of the predetermined bit pattern is associated with the known position of the magnetic storage medium. A current positional index bit is read from the magnetic storage medium and a positional bit sequence comprising the current positional index bit is formed. The positional bit sequence is compared with the predetermined bit pattern and, based on the comparison, whether the position of the magnetic medium is the known position can be determined.Type: GrantFiled: June 23, 1999Date of Patent: December 4, 2001Assignee: Iomega CorporationInventor: Marvin R. DeForest
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Patent number: 6320712Abstract: A highly reliable, low overhead method for determining a rotational position of a magnetic storage medium that is divided into a plurality of servo sections is provided. The inventive method includes defining a predetermined bit pattern that corresponds to a known position of the magnetic storage medium. A rotational position indicator bit is associated with each servo sector such that a known bit of the predetermined bit pattern is associated with the known position of the magnetic storage medium. A current rotational position indicator bit is read from the magnetic storage medium and a rotational position bit sequence comprising the current rotational position indicator bit is formed. The rotational position bit sequence is compared with the predetermined bit pattern and, based on the comparison, whether the rotational position of the magnetic medium is the known rotational position can be determined.Type: GrantFiled: August 11, 1999Date of Patent: November 20, 2001Assignee: Iomega CorporationInventor: Marvin R. DeForest
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Patent number: 4376974Abstract: An associative memory system including a plurality of associative data controllers (ADCs) which operate in parallel upon a mass storage including a storage array for each ADC. A primitive function processor (PFP) couples the ADCs to a control unit which provides user access to the system. Hardware instructions are issued by the PFP to the ADCs to enable them to operate in parallel. The ADCs have circuits for performing simultaneous read/write operations with their related storage arrays, and for performing tagging operations, minimum/maximum operations, and logical operations.Type: GrantFiled: March 31, 1980Date of Patent: March 15, 1983Assignee: NCR CorporationInventors: John W. Stewart, Darrell W. Woelk, Marvin R. DeForest