Patents by Inventor Marvin Rosalejos Gestole

Marvin Rosalejos Gestole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7906837
    Abstract: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: March 15, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Elsie Agdon Cabahug, Marvin Rosalejos Gestole, Margie Sebial Tumulak-Rios, Lilith U. Montayre, Romel N. Manatad
  • Patent number: 7560311
    Abstract: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: July 14, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Elsie Agdon Cabahug, Marvin Rosalejos Gestole, Margie Sebial Tumulak-Rios, Lilith U. Montayre, Romel N. Manatad
  • Patent number: 7122884
    Abstract: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: October 17, 2006
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Elsie Agdon Cabahug, Marvin Rosalejos Gestole, Margie Sebial Tumulak-Rios, Lilith U. Montayre, Romel N. Manatad