Abstract: Generating test input includes initializing a current pseudo-random value at a test input generator coupled to a circuit component. Write data is received from the circuit component. The following are repeated to generate next pseudo-random values as test input. The current pseudo-random value and the write data are retrieved. A next pseudo-random value is generated from the current pseudo-random value and the write data according to a generation function. The next pseudo-random value is transferred to the circuit component as the test input.

Abstract: Providing clock signals includes receiving a first clock signal at a first clock circuit and at a second clock circuit, where the first clock signal comprises first cycles. A second clock signal is generated from the first clock signal at the first clock circuit, where the second clock signal comprises second cycles and a first cycle corresponds to a first multiple of the second cycles. A third clock signal is generated from the first clock signal at the second clock circuit, where the third clock signal comprises third cycles and a second cycle corresponds to a second multiple of the third cycles. The first clock signal and the second clock signal are sampled using the third clock signal. A safe cycle is determined in response to the sampled clock signals. Data is transferred in accordance with the safe cycle.

Abstract: Synchronizing output from timed circuits includes receiving a first clock signal having a first frequency at a first timed circuit. A first sequence of first circuit values is retrieved from the first timed circuit, and first count values are periodically inserted into the first sequence using a first counter. A second clock signal having a second frequency is received at a second timed circuit, where the first frequency corresponds to a multiple of the second frequency. A second sequence of second circuit values is retrieved from the second timed circuit and second count values are periodically inserted into the second sequence using a second counter. The first sequence can be synchronized with the second sequence according to the first count values, the second count values, and the multiple.

Abstract: A CPU-Peripheral bus interface for 64-bit local bus to 32-bit peripheral bus uses byte enable signaling to provide byte lane steering. Qbuffer logic provides a hardware interface that interfaces directly to the processor local-bus--a Qbuffer protocol using conventional byte enable signals provides lane steering to eliminate the need for separate multiplexing logic. The Qbuffer protocol signals include a BE control signal asserted by the system logic to cause the CPU to relinquish control of the byte enable control lines, such that the system control logic is able to drive the BE control lines with byte enable codes to implement lane steering for CPU-Peripheral transfers.

Abstract: A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery counter comprises a clock input from the processor and a signal derived from the bus control signal READY. The I/O recovery counter begins to count at the receipt of the READY signal after the initiation of an I/O bus cycle. The bus interface unit waits until the I/O recovery counter completes its count of the I/O recovery period prior to initiating another I/O bus cycle.

Abstract: An input buffer circuit provides programmable resistors for inputs to a microprocessor and compensates for switching voltage timing differences caused when a selected programmable resistor is utilized for a selected input. In a preferred embodiment, an input buffer circuit has a weak transistor coupled between the input and an operating voltage source or ground, and a compensation circuit including two transistors in series between the operating voltage source or ground, and an output. When the weak transistor is on, thereby raising or lowering the input signal, one of the transistors is also on and the other transistor couples the output to the operating voltage source or ground.

Abstract: A procedure for implementing cache line replacement cycle as split replacement cycles is used in a 64/32 computer system including a 64-bit x86 microprocessor interfaced to a 32-bit x86 bus architecture which does not support pipelined bus cycles. The microprocessor includes an internal L1 cache with two sectors S0 and S1 per cache line such that a cache line replacement request involving both sectors is performed as a split replacement cycle with a separate burst write cycle for each sector. The microprocessor's bus interface unit (BIU) includes (a) a BCC register which is used to stage the first sector (S0) of a split replacement cycle as the current bus cycle, and (b) a BNC register, which is used in a pipelined 64-bit bus architecture to stage pipelined bus cycles, but is used in the exemplary 64/32 system to stage the second sector (S1) of the split replacement cycle.

Abstract: A single block bus transfer (SCBT) protocol is implemented, in an exemplary embodiment, in a computer system that includes an .times.86 microprocessor, system logic, and an external memory subsystem including L2 cache and system DRAM, intercoupled by a 586 bus architecture. The microprocessor's bus interface unit (BIU) includes SCBT logic that generates internal effective BRDY# and the effective KEN# signals from either (a) L2.sub.-- HIT from the L2 cache, or (b) BRDY# or KEN# from the system logic. The effective KEN# signal is used for convert a potentially cacheable read into a burst fill cycle. The exemplary L2 cache is able to perform address decode and cache look-up in time to return L2 HIT to the processor during the ADS# clock with sufficient timing margin to permit the processor to complete the bus transfer (either not burst bus cycle, or the first bus transfer of a burst cycle) in that clock and set up for a next bus transfer in the next clock.

Abstract: A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data, and includes an X%DIRTY latency-control function. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away).