Abstract: In some embodiments, a circuit may include an input configured to receive a signal and a radix-r input/output pruning fast Fourier transform (FFT) processing element coupled to the input. The radix-r input/output pruning FFT processing element may be configured to remove FFT operations on input values of zero within the signal and to determine a discrete Fourier Transform (DFT) output having fewer output values than a number of input values of the signal.

Abstract: In some embodiments, a circuit may include an input configured to receive a signal and a radix-23 fast Fourier transform (FFT) processing element coupled to the input. The radix-23 FFT processing element may be configured to control variation of twiddle factors during calculation of a complete FFT through a plurality of processing stages. The radix-23 FFT processing element may be configured to incorporate the twiddle factors and adder tree matrices of the calculation into a single stage.

Abstract: In some embodiments, a circuit may include an input configured to receive a signal and a radix-r fast Fourier transform (FFT) processing element coupled to the input. The radix-r FFT processing element may be configured to subdivide data of size N into r equal sub-domains of size N/r?1 to determine specific frequencies.

Abstract: In some embodiments, an apparatus can include a memory configured to store data at a plurality of addresses and a generalized radix-r fast Fourier transform (FFT) processor configured to determine a plurality of FFTs for any positive integer Discrete Fourier Transform (DFT) by utilizing three counters to access the data and the coefficient multipliers at each stage of the FFT processor.

Abstract: In some embodiments, an apparatus may include a memory configured to store data at a plurality of addresses and a processor circuit including a plurality of processor cores. Each processor core may include multiple threads. The processor circuit may be configured to subdivide an input data stream into a plurality of three-dimensional matrices corresponding to a number of processor cores of the processor circuit. The processor circuit may be further configured to associate each matrix with a respective one of the plurality of processor cores and determine concurrently a three-dimensional FFT for each matrix of the plurality of three-dimensional matrices within the respective one of the plurality of processor cores to produce an FFT output.

Abstract: The present invention is two-iteration Fourier transform processor for performing Fourier transform of N data inputs into N data outputs. The processor comprises a plurality of two-iteration radix-r modules and a combination phase element. Each radix-r module comprises r radix-r butterflies, a feedback network and a plurality of switches. Each radix-r butterfly comprises r inputs and outputs and a butterfly processing element. The butterfly processing element includes a plurality of multipliers for multiplying the input data and corresponding coefficients and an adder for summing the multiplication outputs from the multipliers. The feedback network feeds outputs of the radix-r butterflies to the corresponding inputs of the radix-r butterfly and the switches selectively pass the input data or the feedback, alternately, to the corresponding radix-r butterfly. The combination phase element includes at least one stage of butterfly computing elements for combining the outputs from the r radix-r butterfly.

Abstract: The present invention is related to a method and apparatus for enhancing processing speed for performing a least mean square operation by parallel processing. The input data are subdivided into a plurality of groups and processed by a plurality of adaptive filters in parallel. A Jaber product device is utilized for rearranging the processing results. A subtractor subtracts the output from the Jaber product device from a desired result to generate an error signal. A feedback network adjusts the adaptive filters in accordance with the error signal.

Abstract: The present invention is related to a method and apparatus for a robust adaptive algorithm for adjusting coefficients of an adaptive filter and a robust Voice Activity Detector (VAD) which are used in Active Noise Suppressor (ANS). The Filtered Least Mean Squares (LMS) algorithm, which is widely used in digital signal processing, is deployed along with the VAD to reduce the effect of noise in a noisy environment. The present invention guarantees stability of the Filtered LMS algorithm and the VAD, which could be deployed in underground communication system. Numerical simulations and experimentally obtained results exhibit significant improvement on convergence and stability of the proposed adaptive algorithm with application to active noise suppressors.

Abstract: The present invention is related to a method and apparatus for voice activity detection (VAD) in which a set of measurements are made over the interval of a processed frame, and which are used to determine if segments of the frame contain voiced or unvoiced signals. The proposed measurements include the mean of the log energy of noise over the time, the zero crossing count, and the autocorrelation coefficient. The present invention may be used in speech enhancement or signal de-noising applications.

Abstract: The present invention is related to a method and apparatus for enhancing processing speed for performing a least mean square operation by parallel processing. The input data are subdivided into a plurality of groups and processed by a plurality of adaptive filters in parallel. A Jaber product device is utilized for rearranging the processing results. A subtractor subtracts the output from the Jaber product device from a desired result to generate an error signal. A feedback network adjusts the adaptive filters in accordance with the error signal.

Abstract: An address generator for use in conjunction with a fast Fourier transform processor includes an efficient architecture for computing the memory addresses of input data points, output data points and twiddle coefficients. In particular, multiplication operation in the calculation of memory addresses is minimized. Instead, a cascaded series of adders is used, in which the output of one adder is input to the next adder. At each stage of the cascaded adders, the same input variable is successively added. The cascaded adder structure is used in the writing address generator, the reading address generator and the twiddle coefficient address generator. In addition, a plurality of modulo N circuits is used in series with the cascaded series of adders to generate the twiddle coefficient addresses.

Abstract: The present invention is two-iteration Fourier transform processor for performing Fourier transform of N data inputs into N data outputs. The processor comprises a plurality of two-iteration radix-r modules and a combination phase element. Each radix-r module comprises r radix-r butterflies, a feedback network and a plurality of switches. Each radix-r butterfly comprises r inputs and outputs and a butterfly processing element. The butterfly processing element includes a plurality of multipliers for multiplying the input data and corresponding coefficients and an adder for summing the multiplication outputs from the multipliers. The feedback network feeds outputs of the radix-r butterflies to the corresponding inputs of the radix-r butterfly and the switches selectively pass the input data or the feedback, alternately, to the corresponding radix-r butterfly. The combination phase element includes at least one stage of butterfly computing elements for combining the outputs from the r radix-r butterfly.

Abstract: The present invention is single-iteration Fourier transform processor. A Fourier transform processor performs Fourier transform of N input data into N output data with a radix-r butterfly. The Fourier transform processor includes N/r radix-r modules. Each radix-r module includes a plurality of radix-r engines, and each radix-r engine includes a plurality of multipliers for multiplying each of the data inputs and corresponding coefficients, an adder for adding the multiplication results and an accumulator for accumulating the multiplication results to generate a Fourier transform output. By accumulating the processing results instead storing intermediate results, the present invention reduces memory access times. More than one radix-r engines may be utilized in parallel to generate one output, or N radix-r engines may be used in maximum parallel processing.

Abstract: The discrete Fourier transform (DFT) is computed in a plurality of parallel processors. A DFT of length N is divided into r partial DFTs of length (N/r), in which the r partial DFTs are calculated in separate parallel processors and then combined in a combination phase to form a complete DFT of length (N). The r partial FFTs are able to be computed in parallel multiprocessors by defining the mathematical model of the combination phase in such manner so as to allow the r parallel processors to operate independently and simultaneously. A second embodiment presents a radix-r fast Fourier algorithm that reduces the computational effort as measured by the number of multiplications and permits the N/r parallel processors to operate simultaneously and with a single instruction sequence.

Abstract: A Fast Fourier Transformation (FFT) method and apparatus is implemented using a radix-r butterfly design based on a reduced single phase of calculation, termed a butterfly-processing element (BPE). Butterfly calculations are each executed in the same number of iterations, and comprised of substantially identical butterfly-processing elements. The resulting algorithm, in which a number of parallel processors operate simultaneously by a single instruction sequence, reduces both the computational burden and the communication burden. The use of substantially identical butterfly-processing elements, repeated in combination to form a radix-r butterfly, enables the design of FFT butterflies containing identical structures and a systematic means of accessing the corresponding multiplier coefficients stored in memory. The butterfly-processing element substantially reduces the complexity of the radix-r butterfly, particularly for higher order radices.

Abstract: An active noise suppression system for use in noisy environments includes a dual microphone noise suppression system in which the echo between the two microphones is substantially canceled or suppressed. Noise is cancelled by the use of first and second line echo cancellers, which model the delay and transmission characteristics of the acoustic path between the two microphones. In a first embodiment, a noise suppression system acts as an ear protector, canceling substantially all or most of the noise striking the dual microphones of the ear set. In a second embodiment, a noise suppression system in accordance with the present invention acts a noise suppression communication system, suppressing background noise while allowing speech signals to be heard by the wearer.

Abstract: An address generator for use in conjunction with a fast Fourier transform processor includes an efficient architecture for computing the memory addresses of input data points, output data points and twiddle coefficients. In particular, multiplication operation in the calculation of memory addresses is minimized. Instead, a cascaded series of adders is used, in which the output of one adder is input to the next adder. At each stage of the cascaded adders, the same input variable is successively added. The cascaded adder structure is used in the writing address generator, the reading address generator and the twiddle coefficient address generator. In addition, a plurality of modulo N circuits is used in series with the cascaded series of adders to generate the twiddle coefficient addresses.

Abstract: The discrete Fourier transform (DFT) is computed in a plurality of parallel processors. A DFT of length N is divided into r partial DFTs of length (N/r), in which the r partial DFTs are calculated in separate parallel processors and then combined in a combination phase to form a complete DFT of length (N). The r partial FFTs are able to be computed in parallel multiprocessors by defining the mathematical model of the combination phase in such manner so as to allow the r parallel processors to operate independently and simultaneously. A second embodiment presents a radix-r fast Fourier algorithm that reduces the computational effort as measured by the number of multiplications and permits the N/r parallel processors to operate simultaneously and with a single instruction sequence.

Abstract: A Fast Fourier Transformation (FFT) method and apparatus is implemented using a radix-r butterfly design based on a reduced single phase of calculation, termed a butterfly-processing element (BPE). Butterfly calculations are each executed in the same number of iterations, and comprised of substantially identical butterfly-processing elements. The resulting algorithm, in which a number of parallel processors operate simultaneously by a single instruction sequence, reduces both the computational burden and the communication burden. The use of substantially identical butterfly-processing elements, repeated in combination to form a radix-r butterfly, enables the design of FFT butterflies containing identical structures and a systematic means of accessing the corresponding multiplier coefficients stored in memory. The butterfly-processing element substantially reduces the complexity of the radix-r butterfly, particularly for higher order radices.