Abstract: A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.

Abstract: In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.

Abstract: A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.

Abstract: A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.

Abstract: In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.

Abstract: A semiconductor, silicon-on-oxide (SOI) structure having a silicon layer disposed on a bottom oxide (BOX) insulating layer. A deep trench isolation (DTI) material passes vertically through the silicon layer to the bottom oxide insulating layer. The deep trench isolation material has a lower permittivity than the permittivity of the silicon. A coaxial transmission line having an inner electrical conductor and an outer electrically conductive shield structure disposed around the inner electrical conductor passing vertically through the deep trench isolation material to electrically connect electrical conductors disposed over the bottom oxide insulating layer to electrical conductors disposed under the contacts bottom oxide insulating layer.

Abstract: A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.

Abstract: Directional couplers are provided. In one embodiment, the directional coupler includes first and second transmission line segments positioned on a first plane and spaced apart by a first distance, third and fourth transmission line segments positioned on a second plane and spaced apart by a second distance, the second plane spaced apart from the first plane, a first conductive segment connecting the first and third transmission line segments, and a second conductive segment connecting the second and fourth transmission line segments, where the first and second transmission line segments are configured to couple energy therebetween, and where the third and fourth transmission line segments are configured to couple energy therebetween.

Abstract: Directional couplers are provided. In one embodiment, the directional coupler includes first and second transmission line segments positioned on a first plane and spaced apart by a first distance, third and fourth transmission line segments positioned on a second plane and spaced apart by a second distance, the second plane spaced apart from the first plane, a first conductive segment connecting the first and third transmission line segments, and a second conductive segment connecting the second and fourth transmission line segments, where the first and second transmission line segments are configured to couple energy therebetween, and where the third and fourth transmission line segments are configured to couple energy therebetween.

Abstract: A switching circuit. The novel switching circuit includes an active device and a first circuit for providing a reactive inductive load in shunt with the active device. In an illustrative embodiment, the first circuit is implemented using a transmission line coupled between an output of the active device and ground, in parallel with the device, to minimize the parasitic effects of the device drain to source capacitance. In a preferred embodiment, the active device includes a silicon-germanium NFET optimized for operation at high frequencies (e.g. up to 20 GHz). The optimization process includes coupling a compact, low-parasitic polysilicon resistor to a gate of the NFET to provide gate RF isolation, and designing the gate manifold, drain manifold, and drain to source spacing of the NFET for optimal high frequency operation.

Abstract: A switching circuit. The novel switching circuit includes an active device and a first circuit for providing a reactive inductive load in shunt with the active device. In an illustrative embodiment, the first circuit is implemented using a transmission line coupled between an output of the active device and ground, in parallel with the device, to minimize the parasitic effects of the device drain to source capacitance. In a preferred embodiment, the active device includes a silicon-germanium NFET optimized for operation at high frequencies (e.g. up to 20 GHz). The optimization process includes coupling a compact, low-parasitic polysilicon resistor to a gate of the NFET to provide gate RF isolation, and designing the gate manifold, drain manifold, and drain to source spacing of the NFET for optimal high frequency operation.