Abstract: A method comprising forming a trench in a substrate and forming a first Ti layer on the top surface of the substrate, such that, the first Ti layer is formed on the exposed surface of the trench. Forming a Nb layer on an exposed top surface of first Ti layer and forming a second Ti layer on the exposed top surface of the Nb layer. Planarizing the second Ti layer, the Nb layer, and the first Ti layer to the top surface of the substrate, wherein the second Ti layer, the Nb layer, and the first Ti layer remain within the trench, wherein the Nb layer has at least two surfaces exposed during the planarizing process.

Abstract: A method comprising forming capacitor pads for a qubit on a silicon wafer. Applying a resist layer on top of the capacitor pads. Pattern the resist layer to expose a portion of the capacitor pads. Utilizing an electron beam to remove the exposed portion of the capacitor.

Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.

Abstract: A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions.

Abstract: A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at least one substantially present element having an atomic number at least 5 greater than a highest atomic number substantially present element within materials surrounding the alignment mark Also included within the microelectronic structure is a dual damascene aperture located within the dielectric layer. The dual damascene aperture may be fabricated using, among other methods, a hybrid lithography method that uses direct write lithography and optical lithography, in conjunction with the at least one alignment mark and an electron beam as an alignment beam.

Abstract: A microelectronic structure, and in particular a semiconductor structure, includes a substrate that includes an alignment mark comprising a substantially present element that has an atomic number at least 5 greater than a highest atomic number substantially present element within the substrate. Alignment to the alignment mark may be effected using an electron beam as an alignment beam with respect to both a direct write exposure and a reticle filtered optical exposure of a mask layer (i.e., photoresist mask layer) located over the alignment mark and the substrate. The electron beam alignment beam may effectively penetrate through other layers, including conductor layers comprising elements having appropriately low atomic number, located interposed between the alignment mark and the mask layer.

Abstract: A method of forming a semiconductor device includes forming a first interlevel dielectric (ILD) layer over one or more transistor structures formed on a substrate, the one or more transistor structures including an active area, source/drain contact and a gate conductor formed over the substrate; forming a first metal (M1) level trench in an upper portion of the first ILD layer, followed by forming vias in a lower portion of the first ILD layer, down to the source/drain contact and down to the gate conductor; and filling both the trench and vias with a conductive material, thereby resulting in a dual damascene metal process at and below the M1 level of the semiconductor device.

Abstract: A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions.

Abstract: A microelectronic structure, and in particular a semiconductor structure, includes a substrate that includes an alignment mark comprising a substantially present element that has an atomic number at least 5 greater than a highest atomic number substantially present element within the substrate. Alignment to the alignment mark may be effected using an electron beam as an alignment beam with respect to both a direct write exposure and a reticle filtered optical exposure of a mask layer (i.e., photoresist mask layer) located over the alignment mark and the substrate. The electron beam alignment beam may effectively penetrate through other layers, including conductor layers comprising elements having appropriately low atomic number, located interposed between the alignment mark and the mask layer.

Abstract: A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at least one substantially present element having an atomic number at least 5 greater than a highest atomic number substantially present element within materials surrounding the alignment mark Also included within the microelectronic structure is a dual damascene aperture located within the dielectric layer. The dual damascene aperture may be fabricated using, among other methods, a hybrid lithography method that uses direct write lithography and optical lithography, in conjunction with the at least one alignment mark and an electron beam as an alignment beam.

Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.

Abstract: A process of making a microcontact printing stamp useful in the microcontact printing of a microcircuit. In this process an elastomeric microcontact printing stamp is formed by curing a degassed liquid elastomeric monomer or oligomer, optionally saturated with helium, a mixture of helium and an inert gas or a mixture of hydrogen and an inert gas, in a mold in which a photoresist master, defining a microcircuit in negative relief, is predisposed above a backplane.

Abstract: A process of making a high precision microcontact printing stamp in which an elastomeric monomer or oligomer is introduced into a mold wherein a photoresist master imprinted with a microcircuit design in negative relief is predisposed. The monomer or oligomer is cured at a temperature no higher than about ambient temperature whereby a distortion-free microcontact printing stamp having the microcircuit design of the photoresist master in positive relief is formed.

Abstract: A process of making a microcontact printing stamp useful in the microcontact printing of a microcircuit. In this process an elastomeric microcontact printing stamp is formed by curing a degassed liquid elastomeric monomer or oligomer, optionally saturated with helium, a mixture of helium and an inert gas or a mixture of hydrogen and an inert gas, in a mold in which a photoresist master, defining a microcircuit in negative relief, is predisposed above a backplane.

Abstract: A process of making a microcontact printing stamp useful in microcontact printing of microcircuits. In this process an elastomeric microcontact printing stamp is formed by curing an elastomeric monomer or oligomer in a mold in which a photoresist master, defining a microcircuit in negative relief, is predisposed above a flat and rigid backplane laminate. The flat and rigid plane member of the backplane laminate is delaminated from the backplane after the printing stamp is removed from the mold.

Abstract: A process of making a high precision microcontact printing stamp in which an elastomeric monomer or oligomer is introduced into a mold wherein a photoresist master imprinted with a microcircuit design in negative relief is predisposed. The monomer or oligomer is cured at a temperature no higher than about ambient temperature whereby a distortion-free microcontact printing stamp having the microcircuit design of the photoresist master in positive relief is formed.