Patents by Inventor Mary Breton

Mary Breton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11804378
    Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: October 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Raghuveer R Patlolla, Donald F Canaperi, Cornelius Brown Peethala, Chih-Chao Yang, Mary Breton
  • Publication number: 20230215734
    Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 6, 2023
    Inventors: Raghuveer R. Patlolla, Donald F. Canaperi, Cornelius Brown Peethala, Chih-Chao Yang, Mary Breton
  • Patent number: 11199505
    Abstract: A method for machine learning enhanced optical-based screening for in-line wafer testing includes receiving optical spectra data for a wafer-under-test by performing scatterometry on the wafer-under-test, performing predictive model screening by applying a predictive model based on the optical spectra data, determining whether a device associated with the wafer-under-test is defective based on the predictive model screening, and if the device is determined to be defective, dynamically modifying a yield map associated with the wafer-under-test, including reassigning at least one die.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robin Hsin Kuo Chao, Mary Breton, Huai Huang, Dexin Kong, Lawrence A. Clevenger
  • Publication number: 20200064275
    Abstract: A method for machine learning enhanced optical-based screening for in-line wafer testing includes receiving optical spectra data for a wafer-under-test by performing scatterometry on the wafer-under-test, performing predictive model screening by applying a predictive model based on the optical spectra data, determining whether a device associated with the wafer-under-test is defective based on the predictive model screening, and if the device is determined to be defective, dynamically modifying a yield map associated with the wafer-under-test, including reassigning at least one die.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 27, 2020
    Inventors: Robin Hsin Kuo Chao, Mary Breton, Huai Huang, Dexin Kong, Lawrence A. Clevenger
  • Publication number: 20130054141
    Abstract: A route finding system comprising a memory, GPS device, library of maps, an optimization algorithm and means for capturing user input and outputting data. The user input includes points, goals, constraints and relative preferences. Goals and constraints include characteristics of the route such as the type of road, number of turns, and traffic. The relative preferences are converted into numerical weights, positive or negative. In addition, the system integrates social networks' ratings and comments to further enhance route selection.
    Type: Application
    Filed: August 29, 2012
    Publication date: February 28, 2013
    Applicant: Princeton Satellite Systems
    Inventors: Michael Adam Paluszek, Mary Breton, Stephanie Thomas