Abstract: A serial memory device includes a test mode for accelerating the writing of externally-supplied data into the memory array by ganging column address so that a single clock writes a single row. Data is retrieved from the memory either by singularly addressed locations or by mirrored address locations across a memory boundary with retrieved data being individually compared via logic asserted during testing operations. Depending on the requested test mode, the compare results can return an order for continuance of array testing or insertion of complemented data into the currently-compared memory location and continuance of array testing. A GO/No Go indication is provided via output circuitry controlled by the test mode.

Abstract: A method for accessing data in a serial ferroelectric memory device including an input shift register coupled to a ferroelectric memory array including a plurality of memory cells arranged in a number of rows and columns thereof, the memory array having associated row, column, and segment decoders, includes clocking a serial address into the input shift register and starting a read access before the serial address is completely shifted into the input shift register. A read access can be started before an input bit sequence containing row, column, and segment decoder addresses has been completely clocked into the memory.