Abstract: Techniques regarding lithographic processes for fabricating Josephson junctions are provided. For example, one or more embodiments described herein can comprise a method that can include depositing a first resist layer onto a second resist layer. The first resist layer can include a bridge portion that defines an opening for forming a Josephson junction. The method can also comprise depositing a third resist layer onto the bridge portion. The third resist layer can shield the opening from an angled deposition of a superconducting material during fabrication of the Josephson junction.

Abstract: Techniques regarding lithographic processes for fabricating Josephson junctions are provided. For example, one or more embodiments described herein can comprise a method that can include depositing a first resist layer onto a second resist layer. The first resist layer can include a bridge portion that defines an opening for forming a Josephson junction. The method can also comprise depositing a third resist layer onto the bridge portion. The third resist layer can shield the opening from an angled deposition of a superconducting material during fabrication of the Josephson junction.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Abstract: A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate.

Abstract: A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate.

Abstract: A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate.

Abstract: A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality of vias disposed on the first substrate.

Abstract: A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate.

Abstract: A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate.

Abstract: A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate.

Abstract: A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.

Abstract: A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.