Abstract: The present disclosure relates to systems and methods for scanning refuse (garbage, trash) from a large geographic area to detect the presence of hazardous materials in the refuse. Hazardous material may comprise CBRNE agents, components of terrorist devices, environmental pollutants and toxins and illegal drugs and may include trace particulates of such agents as well as by-products thereof. Systems and methods, according to some embodiments, may further comprise geo-locating to a small geographic area the origin of hazardous material. Accordingly, in some embodiments the disclosure provides systems and methods to geo-locate facilities or addresses where hazardous materials are generated, thereby geo-locating facilities that make terrorist devices, sources of environmental pollutants and/or sources of illegal drugs.

Abstract: The present disclosure relates to systems and methods for scanning refuse (garbage, trash) from a large geographic area to detect the presence of hazardous materials in the refuse. Hazardous material may comprise CBRNE agents, components of terrorist devices, environmental pollutants and toxins and illegal drugs and may include trace particulates of such agents as well as by-products thereof. Systems and methods, according to some embodiments, may further comprise geo-locating to a small geographic area the origin of hazardous material. Accordingly, in some embodiments the disclosure provides systems and methods to geo-locate facilities or addresses where hazardous materials are generated, thereby geo-locating facilities that make terrorist devices, sources of environmental pollutants and/or sources of illegal drugs.

Abstract: A sensor chip assembly time delay integration circuit useful with image sensing arrays uses a duplex bucket brigade circuit (120) with two or more charge transfer paths, a number of capacitors (130, 133, 136) common to the charge transfer paths, and a number of capacitors (131, 132, 134, 135) specific to each of the charge transfer paths. Each of the charge transfer paths has a number of MOSFET transfer gates (122, 124, 126, 128; 123, 125, 127, 129) connected in series, and the common capacitors and the path-specific capacitors are alternately connected to the paths. Each of the common capacitors is controllably connected (112, 115, 118) either to a unit cell input circuit (113, 116, 119). a reset node (111, 114, 117), or an open circuit. The circuit operates by storing accumulated image sensor charges from alternate sensor lines on the path-specific capacitors. The common capacitors are reset and then connected to the unit cell input circuits to acquire a first set of image sensor charges.

Abstract: A time delay integration circuit in which a number of unit cell inputs (101, 103, 105, 107) along with their respective switches (170, 171, 172, 173) are input to a bi-directional BBD circuit (110). The BBD circuit performs an SCA TDI with reduced ROIC circuitry and compatibility with standard LSI processing. The bi-directional BBD circuit has numerous pairs of MOSFETs (111, 112; 113, 114; 115, 116; 117, 118; 119, 120; 121, 122; 123, 124; 125, 126; 127, 128; 129, 130; 131, 132; 133, 134; 135, 136; 137, 138; 139, 140; 141, 142) connected in series and numerous storage capacitors (151, 152,153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166) having one of their terminals respectively connected between each of the MOSFET pairs and the other of their terminals alternately connected to clock phases Ø1 and Ø2.

Abstract: An amplifier circuit, referred to as a charge mode capacitor transimpedance amplifier (or CM-CTIA) an input node (IN) and an output node (OUT), and includes a transistor (M.sub.IN) having a gate terminal (G) coupled to the input node, a source terminal (S), and a drain terminal (D) coupled to the output node, a first capacitance (C.sub.FB) coupled between the gate terminal and the drain terminal, a second capacitance (C.sub.S) coupled between the source terminal and a first potential (GND), a third capacitance (C.sub.D) coupled between the drain terminal and the first potential or another fixed potential, a first switch (SW1) coupled between a second potential and the drain terminal, and a second switch (SW2) coupled between a third potential (V.sub.RESET) and the gate terminal. During use, the input node is coupled to an output of a radiation detector, such as a photovoltaic IR detector (12) that forms one element or pixel of an array of IR detectors.

Abstract: An ultra low power gain circuit (UGC) implements a unique operational mode of a source follower circuit, and enables programmable gains greater than unity. A MOSFET has a gate terminal coupled to an input capacitance (Cin). A potential at a drain of the MOSFET is clocked to enable charge to flow through the channel. This charge charges a capacitor (Cout) that is connected to a source of the MOSFET. After charging Cout, the drain potential is restored to an initial value, and the charge on Cout discharges back through the MOSFET until the source voltage is one threshold drop from the gate potential, at which time the MOSFET turns off. Cout then stops discharging, and the final voltage appearing on Cout is a function of the magnitude of the gate voltage appearing on Cin. As the voltage at the source of the MOSFET changes, capacitive coupling, via (Cgs) to the gate, causes the gate voltage to also change. The value of the gate voltage determines a magnitude of a final voltage to which the source settles.

Abstract: An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal.

Abstract: A blocked impurity band detector having a high fill factor is comprised of a radiation detecting layer and an overlying blocking layer which are interposed between a plurality of rear contact regions and a frontside common electrical contact layer. Disposed over the surface of the frontside contact layer is a layer of metalization formed as a substantially transparent grid. Radiation enters the detecting layer through the grid, contact layer, and blocking layer. Each of the rear contact regions is conductively coupled to an end of a metallic conductor, or via, which is disposed through an insulating substrate. The opposite end of each of the metallic conductors exits the back surface of the substrate and is adapted for connection to an integrated circuit readout device.

Abstract: A system 10 for imaging radiation received from a scene provides for the focusing of the radiation upon a set of detectors 12. A set of amplifiers 14 couple the detectors to an image processor 24 for forming an image of the scene. The amplifiers are pulsed with a repeating sequence of pulses providing sequential operation of the amplifiers. The amplifiers and the detectors are constructed on a single substrate which is cyrogenically cooled for improved signal-to-noise ratio. Amplifying elements in each of the amplifiers are powered by energy stored as electric charges in capacitors. The capacitors are recharged with pulses from a pulsing unit repetitively in a repeating sequence of amplifier operation. The capacitors provide for integration of detector signals, there being additional integration performed at the front end of each of the amplifiers utilizing stray capacitance and detector capacitance.

Abstract: An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal.

Abstract: A new technique, and output encoding circuits using that technique, are disclosed for interfacing between a semiconductor IR detector 23 and associated output electronics 24, 25, 26, which technique and circuits transfer a charge packet onto a sense capacitor 22 that previously stored a reset level signal. The resulting stepped signal change, or delta, in the voltage present on that capacitor 22 is employed as the output signal.

Abstract: A new technique, and output encoding circuits using that technique, are disclosed for interfacing between a semiconductor IR detector 23 and associated output electronics 24, 25, 26 which technique and circuits transfer a charge packet onto a sense capacitor 22 that previously stored a reset level signal. The resulting stepped signal change, or delta, in the voltage present on that capacitor 22 is employed as the output signal.

Abstract: Noise reduction and dynamic range expansion in a CCD imager is achieved by combining a narrow FAT zero metering gate with a reference column subtraction and CCD charge bailing.