Abstract: The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, where Vth represents the threshold voltage of the transfer devices of the SRAM cells. This prevents the body regions of the transfer devices of each cell of the array from fully charging up, and thus the system avoids the parasitic bipolar leakage current effects attributed to devices fabricated on a partially-depleted SOI substrate. Also, during idle or sleep mode, if all the bitlines are kept at about the Vdd minus Vth voltage level, power consumption by the SRAM architecture system is decreased. This is because the leakage path via one of the transfer gates of all the SRAM cells is greatly minimized.

Abstract: Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.

Abstract: Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.

Abstract: A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.

Abstract: A simple method of making a thin film transistor (TFT) on a substrate with an insulating surface layer is disclosed. A layer of dopant source layer is deposited on the insulating layer, followed by defining a gate stack consisting of a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon.

Abstract: A thick-oxide ESD transistor for a BiCMOS integrated circuit has its source/drain contacts formed of the BiCMOS base or emitter polysilicon and its source/drain formed by an outdiffusion of the respective polysilicon contact. In one embodiment the BiCMOS resistor doping deepens the ESD source/drains, and in another embodiment the BiCMOS collector reach through doping deepens the ESD source/drains. The entire ESD transistor is fabricated from a standard BiCMOS process without any additional steps, has an area of about 100 square microns, can shunt up to 6000 volts, and has a turn-on time of about 10 picoseconds.

Abstract: An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening.

Abstract: An inexpensive and reliable technique for forming connections to a substrate or buried layer of a semiconductor structure employs a laser to melt a small, selected region of a lightly doped layer and a highly doped underlying layer. Extremely rapid diffusion of impurities and mixing of materials within the liquid phase of the melt quickly creates a uniformly doped conductive region when the melt is allowed to recrystallize.