Patents by Inventor Mary Jane R. Alin

Mary Jane R. Alin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12142548
    Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: November 12, 2024
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Long-Ching Wang, Xiaoguang Zeng, Mary Jane R. Alin, Hailin Zhou, Guobing Shen
  • Publication number: 20230215783
    Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Long-Ching Wang, Xiaoguang Zeng, Mary Jane R. Alin, Hailin Zhou, Guobing Shen
  • Patent number: 11309233
    Abstract: A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: April 19, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Xiaotian Zhang, Mary Jane R. Alin, Bo Chen, David Brian Oraboni, Jr., Long-Ching Wang, Jian Yin
  • Publication number: 20210082790
    Abstract: A power semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a first metal clip, a second metal clip, an inductor assembly, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. A method for fabricating a power semiconductor package. The method comprises the steps of providing a lead frame; attaching a low side FET and a high side FET to the lead frame; mounting a first metal clip and a second metal clip; mounting an inductor; forming a molding encapsulation; and applying a singulation process.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Xiaotian Zhang, Mary Jane R. Alin, Bo Chen, David Brian Oraboni, JR., Long-Ching Wang
  • Publication number: 20210082793
    Abstract: A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.
    Type: Application
    Filed: February 25, 2020
    Publication date: March 18, 2021
    Inventors: Xiaotian Zhang, Mary Jane R. Alin, Bo Chen, David Brian Oraboni, JR., Long-Ching Wang, Jian Yin
  • Patent number: 10600727
    Abstract: An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RthJC) compared to a conventional IPM.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 24, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Zhiqiang Niu, Bum-Seok Suh, Jun Lu, Son Tran, Wanki Hong, Guobing Shen, Xiaoguang Zeng, Mary Jane R. Alin
  • Publication number: 20190006270
    Abstract: An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RthJC) compared to a conventional IPM.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 3, 2019
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Zhiqiang Niu, Bum-Seok Suh, Jun Lu, Son Tran, Wanki Hong, Guobing Shen, Xiaoguang Zeng, Mary Jane R. Alin