Patents by Inventor Mary Nadeau

Mary Nadeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237643
    Abstract: Heatsinking in laser devices may be improved via a device, including: a header disk having a first face with a circumference; a header post that is thermally conductive, and having: a second face connected to the first face coterminously with the circumference; a third face opposite to the second face; and a fourth face perpendicular to the second face and the third face; a lens holder, having a fifth face connected to the third face; and an optical subassembly connected to the fourth face and optically aligned with the lens holder. The device may also be understood to comprise: a header disk having a circumference; a header post that is thermally conductive, the header post having: an arc coterminous to a portion of the circumference; a mounting face, perpendicular to a plane in which the arc and the circumference are defined; and a bonding face perpendicular to the mounting face.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: February 25, 2025
    Assignee: Cisco Technology, Inc.
    Inventors: Norbert Schlepple, Jock T. Bovington, Mary Nadeau, Mittu Pannala, Jarrett S. Neiman
  • Publication number: 20220368102
    Abstract: Heatsinking in laser devices may be improved via a device, including: a header disk having a first face with a circumference; a header post that is thermally conductive, and having: a second face connected to the first face coterminously with the circumference; a third face opposite to the second face; and a fourth face perpendicular to the second face and the third face; a lens holder, having a fifth face connected to the third face; and an optical subassembly connected to the fourth face and optically aligned with the lens holder. The device may also be understood to comprise: a header disk having a circumference; a header post that is thermally conductive, the header post having: an arc coterminous to a portion of the circumference; a mounting face, perpendicular to a plane in which the arc and the circumference are defined; and a bonding face perpendicular to the mounting face.
    Type: Application
    Filed: May 17, 2021
    Publication date: November 17, 2022
    Inventors: Norbert SCHLEPPLE, Jock T. BOVINGTON, Mary NADEAU, Mittu PANNALA, Jarrett S. NEIMAN
  • Patent number: 10608404
    Abstract: A laser light source, a submount for a semiconductor laser, and a method of providing a laser light source are provided. The laser light source includes a submount with first and second electrical contacts thereon and a trench there-between. A semiconductor laser is bonded to the submount by bonding third and fourth electrical contacts of the laser to the first and second electrical contacts, respectively. The third and fourth electrical contacts of the laser are arranged on opposite side of a laser active stripe, which is arranged over the trench of the submount.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: March 31, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Mary Nadeau, Jarrett S. Neiman, Mittu Pannala
  • Patent number: 10481326
    Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: November 19, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Vipulkumar Patel, Mark Webster, Ravi Tummidi, Mary Nadeau
  • Patent number: 10175448
    Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: January 8, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Mary Nadeau, Vipulkumar Patel, Prakash Gothoskar, John Fangman, John Matthew Fangman, Mark Webster
  • Publication number: 20180233880
    Abstract: A laser light source, a submount for a semiconductor laser, and a method of providing a laser light source are provided. The laser light source includes a submount with first and second electrical contacts thereon and a trench there-between. A semiconductor laser is bonded to the submount by bonding third and fourth electrical contacts of the laser to the first and second electrical contacts, respectively. The third and fourth electrical contacts of the laser are arranged on opposite side of a laser active stripe, which is arranged over the trench of the submount.
    Type: Application
    Filed: February 14, 2017
    Publication date: August 16, 2018
    Inventors: Mary NADEAU, Jarrett S. NEIMAN, Mittu PANNALA
  • Publication number: 20180188450
    Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.
    Type: Application
    Filed: February 19, 2018
    Publication date: July 5, 2018
    Inventors: Vipulkumar PATEL, Mark WEBSTER, Ravi TUMMIDI, Mary NADEAU
  • Patent number: 9933566
    Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 3, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Vipulkumar Patel, Mark Webster, Ravi Tummidi, Mary Nadeau
  • Patent number: 9864133
    Abstract: The embodiments herein describe a photonic chip (formed from a SOI structure) which includes an optical interface for coupling the optical components in the photonic chip to an external optical device. In one embodiment, the optical interface is formed on a separate substrate which is later joined to the photonic chip. Through oxide vias (TOVs) and through silicon vias (TSVs) can be used to electrically couple the optical components in the photonic chip to external integrated circuits or amplifiers. In one embodiment, after the separate wafer is bonded to the photonic chip, a TOV is formed in the photonic chip to electrically connect metal routing layers coupled to the optical components in the photonic chip to a TSV in the separate wafer. For example, the TOV may extend across a wafer bonding interface where the two substrates where bonded to form an electrical connection with the TSV.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: January 9, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Vipulkumar Patel, Mark Webster, Ravi Tummidi, Mary Nadeau
  • Publication number: 20170139142
    Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.
    Type: Application
    Filed: May 2, 2016
    Publication date: May 18, 2017
    Inventors: Vipulkumar PATEL, Mark WEBSTER, Ravi TUMMIDI, Mary NADEAU
  • Publication number: 20170139132
    Abstract: The embodiments herein describe a photonic chip (formed from a SOI structure) which includes an optical interface for coupling the optical components in the photonic chip to an external optical device. In one embodiment, the optical interface is formed on a separate substrate which is later joined to the photonic chip. Through oxide vias (TOVs) and through silicon vias (TSVs) can be used to electrically couple the optical components in the photonic chip to external integrated circuits or amplifiers. In one embodiment, after the separate wafer is bonded to the photonic chip, a TOV is formed in the photonic chip to electrically connect metal routing layers coupled to the optical components in the photonic chip to a TSV in the separate wafer. For example, the TOV may extend across a wafer bonding interface where the two substrates where bonded to form an electrical connection with the TSV.
    Type: Application
    Filed: July 13, 2016
    Publication date: May 18, 2017
    Inventors: Vipulkumar PATEL, Mark WEBSTER, Ravi TUMMIDI, Mary NADEAU
  • Publication number: 20170003463
    Abstract: Embodiments disclosed herein generally relate to a method for manufacturing a photonic device that facilitates precise alignment of a laser with a waveguide. The method generally includes disposing the laser on a support member on a substrate such that the laser contacts the support member. The support member may extend in a direction perpendicular to a base plane of the substrate, and solder may be disposed on the base plane such that a height of the solder in the direction perpendicular to the base plane is less than a height of the support member so that a gap is created between the solder and the laser. Once the laser has been properly aligned with the waveguide, the solder may be heated (e.g., reflowed) so that the solder contacts the laser.
    Type: Application
    Filed: July 2, 2015
    Publication date: January 5, 2017
    Inventors: Mary NADEAU, Thomas DAUGHERTY, Ravi Sekhar TUMMIDI, Vipulkumar PATEL
  • Patent number: 9341792
    Abstract: An silicon-on-insulator (SOI)-based photonics platform is formed to including a venting structure for encapsulating the active and passive optical components formed on the SOI-based photonics platform. The venting structure is used to allow for the encapsulated components to “breathe” such that water vapor and gasses will pass through the package and not condensate on any of the encapsulated optical surfaces. The venting structure is configured to also to prevent dust, liquids and other particulate material from entering the package.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: May 17, 2016
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Mary Nadeau, John Fangman, Duane Stackhouse, Craig Young, David Piede, Vipulkumar Patel
  • Publication number: 20140362457
    Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.
    Type: Application
    Filed: July 15, 2014
    Publication date: December 11, 2014
    Inventors: Mary NADEAU, Vipulkumar PATEL, Prakash GOTHOSKAR, John FANGMAN, John Matthew FANGMAN, Mark WEBSTER
  • Patent number: 8836100
    Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: September 16, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Mary Nadeau, Vipulkumar Patel, Prakash Gothoskar, John Fangman, John Matthew Fangman, Mark Webster
  • Patent number: 8121450
    Abstract: A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: February 21, 2012
    Assignee: Lightwire, Inc.
    Inventors: Mark Webster, Vipulkumar Patel, Mary Nadeau, Prakash Gothoskar, David Piede
  • Publication number: 20110317958
    Abstract: An silicon-on-insulator (SOI)-based photonics platform is formed to including a venting structure for encapsulating the active and passive optical components formed on the SOI-based photonics platform. The venting structure is used to allow for the encapsulated components to “breathe” such that water vapor and gasses will pass through the package and not condensate on any of the encapsulated optical surfaces. The venting structure is configured to also to prevent dust, liquids and other particulate material from entering the package.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 29, 2011
    Applicant: LIGHTWIRE, INC.
    Inventors: Mary Nadeau, John Fangman, Duane Stackhouse, Craig Young, David Piede, Vipulkumar Patel
  • Publication number: 20110127633
    Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.
    Type: Application
    Filed: November 29, 2010
    Publication date: June 2, 2011
    Applicant: LIGHTWIRE, INC.
    Inventors: Mary Nadeau, Vipulkumar Patel, Prakash Gothoskar, John Fangman, John Matthew Fangman, Mark Webster
  • Patent number: 7556440
    Abstract: A unitary optical receiver assembly is formed to include a V-groove passively aligned with a first aspheric lens (the lens formed along a surface perpendicular to the V-groove). An optical fiber is disposed along the V-groove and is used to bring the received optical signal into the unitary assembly. Upon passing through the first aspheric lens, the received optical signal will intercept a 45° turning mirror wall that directs the signal downward, through a second aspheric lens (also molded in the unitary assembly), and then into a photosensitive device. Advantageously, the photosensitive device is disposed in passive alignment with the second aspheric lens, allowing for a received signal to be coupled from an incoming optical fiber to a photosensitive device without needing any type of active alignment therebetween.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 7, 2009
    Assignee: Lightwire Inc.
    Inventors: Dincer Birincioglu, Rajesh Dighde, Mary Nadeau, David Piede, Wenhong Qin
  • Publication number: 20090162013
    Abstract: A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 25, 2009
    Inventors: Mark Webster, Vipulkumar Patel, Mary Nadeau, Prakash Gothoskar, David Piede