Patents by Inventor Mary Nadeau
Mary Nadeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12237643Abstract: Heatsinking in laser devices may be improved via a device, including: a header disk having a first face with a circumference; a header post that is thermally conductive, and having: a second face connected to the first face coterminously with the circumference; a third face opposite to the second face; and a fourth face perpendicular to the second face and the third face; a lens holder, having a fifth face connected to the third face; and an optical subassembly connected to the fourth face and optically aligned with the lens holder. The device may also be understood to comprise: a header disk having a circumference; a header post that is thermally conductive, the header post having: an arc coterminous to a portion of the circumference; a mounting face, perpendicular to a plane in which the arc and the circumference are defined; and a bonding face perpendicular to the mounting face.Type: GrantFiled: May 17, 2021Date of Patent: February 25, 2025Assignee: Cisco Technology, Inc.Inventors: Norbert Schlepple, Jock T. Bovington, Mary Nadeau, Mittu Pannala, Jarrett S. Neiman
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Publication number: 20220368102Abstract: Heatsinking in laser devices may be improved via a device, including: a header disk having a first face with a circumference; a header post that is thermally conductive, and having: a second face connected to the first face coterminously with the circumference; a third face opposite to the second face; and a fourth face perpendicular to the second face and the third face; a lens holder, having a fifth face connected to the third face; and an optical subassembly connected to the fourth face and optically aligned with the lens holder. The device may also be understood to comprise: a header disk having a circumference; a header post that is thermally conductive, the header post having: an arc coterminous to a portion of the circumference; a mounting face, perpendicular to a plane in which the arc and the circumference are defined; and a bonding face perpendicular to the mounting face.Type: ApplicationFiled: May 17, 2021Publication date: November 17, 2022Inventors: Norbert SCHLEPPLE, Jock T. BOVINGTON, Mary NADEAU, Mittu PANNALA, Jarrett S. NEIMAN
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Patent number: 10608404Abstract: A laser light source, a submount for a semiconductor laser, and a method of providing a laser light source are provided. The laser light source includes a submount with first and second electrical contacts thereon and a trench there-between. A semiconductor laser is bonded to the submount by bonding third and fourth electrical contacts of the laser to the first and second electrical contacts, respectively. The third and fourth electrical contacts of the laser are arranged on opposite side of a laser active stripe, which is arranged over the trench of the submount.Type: GrantFiled: February 14, 2017Date of Patent: March 31, 2020Assignee: Cisco Technology, Inc.Inventors: Mary Nadeau, Jarrett S. Neiman, Mittu Pannala
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Patent number: 10481326Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.Type: GrantFiled: February 19, 2018Date of Patent: November 19, 2019Assignee: Cisco Technology, Inc.Inventors: Vipulkumar Patel, Mark Webster, Ravi Tummidi, Mary Nadeau
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Patent number: 10175448Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.Type: GrantFiled: July 15, 2014Date of Patent: January 8, 2019Assignee: Cisco Technology, Inc.Inventors: Mary Nadeau, Vipulkumar Patel, Prakash Gothoskar, John Fangman, John Matthew Fangman, Mark Webster
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Publication number: 20180233880Abstract: A laser light source, a submount for a semiconductor laser, and a method of providing a laser light source are provided. The laser light source includes a submount with first and second electrical contacts thereon and a trench there-between. A semiconductor laser is bonded to the submount by bonding third and fourth electrical contacts of the laser to the first and second electrical contacts, respectively. The third and fourth electrical contacts of the laser are arranged on opposite side of a laser active stripe, which is arranged over the trench of the submount.Type: ApplicationFiled: February 14, 2017Publication date: August 16, 2018Inventors: Mary NADEAU, Jarrett S. NEIMAN, Mittu PANNALA
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Publication number: 20180188450Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.Type: ApplicationFiled: February 19, 2018Publication date: July 5, 2018Inventors: Vipulkumar PATEL, Mark WEBSTER, Ravi TUMMIDI, Mary NADEAU
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Patent number: 9933566Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.Type: GrantFiled: May 2, 2016Date of Patent: April 3, 2018Assignee: Cisco Technology, Inc.Inventors: Vipulkumar Patel, Mark Webster, Ravi Tummidi, Mary Nadeau
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Patent number: 9864133Abstract: The embodiments herein describe a photonic chip (formed from a SOI structure) which includes an optical interface for coupling the optical components in the photonic chip to an external optical device. In one embodiment, the optical interface is formed on a separate substrate which is later joined to the photonic chip. Through oxide vias (TOVs) and through silicon vias (TSVs) can be used to electrically couple the optical components in the photonic chip to external integrated circuits or amplifiers. In one embodiment, after the separate wafer is bonded to the photonic chip, a TOV is formed in the photonic chip to electrically connect metal routing layers coupled to the optical components in the photonic chip to a TSV in the separate wafer. For example, the TOV may extend across a wafer bonding interface where the two substrates where bonded to form an electrical connection with the TSV.Type: GrantFiled: July 13, 2016Date of Patent: January 9, 2018Assignee: Cisco Technology, Inc.Inventors: Vipulkumar Patel, Mark Webster, Ravi Tummidi, Mary Nadeau
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Publication number: 20170139142Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.Type: ApplicationFiled: May 2, 2016Publication date: May 18, 2017Inventors: Vipulkumar PATEL, Mark WEBSTER, Ravi TUMMIDI, Mary NADEAU
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Publication number: 20170139132Abstract: The embodiments herein describe a photonic chip (formed from a SOI structure) which includes an optical interface for coupling the optical components in the photonic chip to an external optical device. In one embodiment, the optical interface is formed on a separate substrate which is later joined to the photonic chip. Through oxide vias (TOVs) and through silicon vias (TSVs) can be used to electrically couple the optical components in the photonic chip to external integrated circuits or amplifiers. In one embodiment, after the separate wafer is bonded to the photonic chip, a TOV is formed in the photonic chip to electrically connect metal routing layers coupled to the optical components in the photonic chip to a TSV in the separate wafer. For example, the TOV may extend across a wafer bonding interface where the two substrates where bonded to form an electrical connection with the TSV.Type: ApplicationFiled: July 13, 2016Publication date: May 18, 2017Inventors: Vipulkumar PATEL, Mark WEBSTER, Ravi TUMMIDI, Mary NADEAU
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Publication number: 20170003463Abstract: Embodiments disclosed herein generally relate to a method for manufacturing a photonic device that facilitates precise alignment of a laser with a waveguide. The method generally includes disposing the laser on a support member on a substrate such that the laser contacts the support member. The support member may extend in a direction perpendicular to a base plane of the substrate, and solder may be disposed on the base plane such that a height of the solder in the direction perpendicular to the base plane is less than a height of the support member so that a gap is created between the solder and the laser. Once the laser has been properly aligned with the waveguide, the solder may be heated (e.g., reflowed) so that the solder contacts the laser.Type: ApplicationFiled: July 2, 2015Publication date: January 5, 2017Inventors: Mary NADEAU, Thomas DAUGHERTY, Ravi Sekhar TUMMIDI, Vipulkumar PATEL
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Patent number: 9341792Abstract: An silicon-on-insulator (SOI)-based photonics platform is formed to including a venting structure for encapsulating the active and passive optical components formed on the SOI-based photonics platform. The venting structure is used to allow for the encapsulated components to “breathe” such that water vapor and gasses will pass through the package and not condensate on any of the encapsulated optical surfaces. The venting structure is configured to also to prevent dust, liquids and other particulate material from entering the package.Type: GrantFiled: June 7, 2011Date of Patent: May 17, 2016Assignee: CISCO TECHNOLOGY, INC.Inventors: Mary Nadeau, John Fangman, Duane Stackhouse, Craig Young, David Piede, Vipulkumar Patel
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Publication number: 20140362457Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.Type: ApplicationFiled: July 15, 2014Publication date: December 11, 2014Inventors: Mary NADEAU, Vipulkumar PATEL, Prakash GOTHOSKAR, John FANGMAN, John Matthew FANGMAN, Mark WEBSTER
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Patent number: 8836100Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.Type: GrantFiled: November 29, 2010Date of Patent: September 16, 2014Assignee: Cisco Technology, Inc.Inventors: Mary Nadeau, Vipulkumar Patel, Prakash Gothoskar, John Fangman, John Matthew Fangman, Mark Webster
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Patent number: 8121450Abstract: A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.Type: GrantFiled: December 11, 2008Date of Patent: February 21, 2012Assignee: Lightwire, Inc.Inventors: Mark Webster, Vipulkumar Patel, Mary Nadeau, Prakash Gothoskar, David Piede
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Publication number: 20110317958Abstract: An silicon-on-insulator (SOI)-based photonics platform is formed to including a venting structure for encapsulating the active and passive optical components formed on the SOI-based photonics platform. The venting structure is used to allow for the encapsulated components to “breathe” such that water vapor and gasses will pass through the package and not condensate on any of the encapsulated optical surfaces. The venting structure is configured to also to prevent dust, liquids and other particulate material from entering the package.Type: ApplicationFiled: June 7, 2011Publication date: December 29, 2011Applicant: LIGHTWIRE, INC.Inventors: Mary Nadeau, John Fangman, Duane Stackhouse, Craig Young, David Piede, Vipulkumar Patel
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Publication number: 20110127633Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.Type: ApplicationFiled: November 29, 2010Publication date: June 2, 2011Applicant: LIGHTWIRE, INC.Inventors: Mary Nadeau, Vipulkumar Patel, Prakash Gothoskar, John Fangman, John Matthew Fangman, Mark Webster
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Patent number: 7556440Abstract: A unitary optical receiver assembly is formed to include a V-groove passively aligned with a first aspheric lens (the lens formed along a surface perpendicular to the V-groove). An optical fiber is disposed along the V-groove and is used to bring the received optical signal into the unitary assembly. Upon passing through the first aspheric lens, the received optical signal will intercept a 45° turning mirror wall that directs the signal downward, through a second aspheric lens (also molded in the unitary assembly), and then into a photosensitive device. Advantageously, the photosensitive device is disposed in passive alignment with the second aspheric lens, allowing for a received signal to be coupled from an incoming optical fiber to a photosensitive device without needing any type of active alignment therebetween.Type: GrantFiled: December 20, 2007Date of Patent: July 7, 2009Assignee: Lightwire Inc.Inventors: Dincer Birincioglu, Rajesh Dighde, Mary Nadeau, David Piede, Wenhong Qin
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Publication number: 20090162013Abstract: A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.Type: ApplicationFiled: December 11, 2008Publication date: June 25, 2009Inventors: Mark Webster, Vipulkumar Patel, Mary Nadeau, Prakash Gothoskar, David Piede