Patents by Inventor Mary P. Luley

Mary P. Luley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7178138
    Abstract: The invention relates to a software system and method for automatically verifying the correct execution of an application ported from one instruction set architecture (ISA) to another ISA. In this method, versions of the application are prepared for the two ISAs. Each version is then executed in a simulator or emulator for the appropriate ISA and the results of any change in memory made during the execution are compared. If each memory change made during the execution of the target version of the application is found to be equivalent to a memory change made during the execution of the source version of the application, the execution of the target (or ported) application is verifiably correct.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: February 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Edward P. Kuzemchak, Christine M. Cipriani, Christophe Favergeon-Borgialli, Mary P. Luley
  • Patent number: 7162618
    Abstract: The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is used to determine if a valid effective address is available for each instruction. If a valid effective address for an instruction is not available, it is computed if possible.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Edward P. Kuzemchak, Christine M. Cipriani, Christophe Favergeon-Borgialli, Mary P. Luley
  • Publication number: 20030088855
    Abstract: The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is used to determine if a valid effective address is available for each instruction. If a valid effective address for an instruction is not available, it is computed if possible.
    Type: Application
    Filed: December 13, 2001
    Publication date: May 8, 2003
    Inventors: Edward P. Kuzemchak, Christine M. Cipriani, Christophe Favergeon-Borgialli, Mary P. Luley
  • Publication number: 20020184613
    Abstract: The invention relates to a software system and method for automatically verifying the correct execution of an application ported from one instruction set architecture (ISA) to another ISA. In this method, versions of the application are prepared for the two ISAs. Each version is then executed in a simulator or emulator for the appropriate ISA and the results of any change in memory made during the execution are compared. If each memory change made during the execution of the target version of the application is found to be equivalent to a memory change made during the execution of the source version of the application, the execution of the target (or ported) application is verifiably correct.
    Type: Application
    Filed: December 13, 2001
    Publication date: December 5, 2002
    Inventors: Edward P. Kuzemchak, Christine M. Cipriani, Christophe Favergeon-Borgialli, Mary P. Luley