Abstract: The invention provides DNA compositions that relate to transgenic insect resistant maize plants. Also provided are assays for detecting the presence of the maize DAS-59122-7 event based on the DNA sequence of the recombinant construct inserted into the maize genome and the DNA sequences flanking the insertion site. Kits and conditions useful in conducting the assays are provided.

Abstract: A monitoring system that is configured to monitor a property is disclosed. The monitoring system includes a sensor that is configured to generate sensor data that indicates an attribute of the property; a floor sensor that is configured to generate floor sensor data that indicates an amount of pressure applied to a portion of a floor of the property; and a monitor control unit. The monitor control unit is configured to receive, from the sensor, the sensor data; receive, from the floor sensor, the floor sensor data; analyze the sensor data and the floor sensor data; and based on analyzing the sensor data and the floor sensor data, perform a monitoring system action.

Abstract: Build-in and portable oral hygiene systems and devices are disclosed which systems and devices effectively function without electricity, batteries, mechanical pumps and motors. Build-in oral hygiene systems may utilize a single set of hot and cold water supply hoses and may be integrated with the faucet as a permanent sink apparatus while portable hygiene devices are manpowered and thus may be used at anytime and anywhere.

Abstract: Techniques for producing integrated capacitors are disclosed. According to one of the techniques, one or more layers are introduced in conjunction with a ground layer supporting a substrate on which various components are realized. Depending on the use of an integrated capacitor, micro capacitors can be formed between one introduced layer and the ground layer or between two introduced layers. As all micro capacitors are connected in parallel, an integrated capacitor with usable capacitance is thus produced without occupying an extra space that would otherwise increase the size of the silicon chip. In addition, with proper connections, an interdigitated capacitor can be formed as well.

Abstract: Techniques for designing high-speed integrated circuits are disclosed. According to one aspect of the present invention, an interpolation circuit is disclosed. A method for designing such an interpolation circuit comprises determining an initial value for all resistors in the interpolation circuit, examining whether outputs from the interpolation circuit are evenly spaced across a predefined range of input signals, and when the outputs are not evenly spaced across a predefined range of input signals, adjusting each of the resistors in reference to the outputs so that the outputs are evenly spaced across a predefined range of input signals.

Abstract: Techniques for producing integrated capacitors are disclosed. According to one of the techniques, one or more layers are introduced in conjunction with a ground layer supporting a substrate on which various components are realized. Depending on the use of an integrated capacitor, micro capacitors can be formed between one introduced layer and the ground layer or between two introduced layers. As all micro capacitors are connected in parallel, an integrated capacitor with usable capacitance is thus produced without occupying an extra space that would otherwise increase the size of the silicon chip. In addition, with proper connections, an interdigitated capacitor can be formed as well.

Abstract: Techniques for implementing transformers with center-taps are described. Based on an overlay winding structure, according to one embodiment, the primary and the secondary of the transformer are respectively formed on two separate layers that are stacked on top of each other, wherein the secondary includes two segments, the two respective terminals of the two segments are coupled together to a component in a circuit to form a center-tap of the secondary. According to another embodiment, three or more separating windings are formed on separate layers. At least one of the windings is a conducting stripe wound in loops and includes a center-tap that extends across but not electrically connected to the loops of the conducting stripe by detouring the conducting stripe through other layers.

Abstract: Techniques for implementing transformers with center-taps are disclosed. Based on an overlay winding structure, according to one embodiment, the primary and the secondary of the transformer are respectively formed on two separate layers that are stacked on top of each other, wherein the secondary includes two segments, the two respective terminals of the two segments are coupled together to a component in a circuit to form a center-tap of the secondary. According to another embodiment, three or more separating windings are formed on separate layers. At least one of the windings is a conducting stripe wound in loops and includes a center-tap that extends across but not electrically connected to the loops of the conducting stripe by detouring the conducting stripe through other layers.

Abstract: A structure and method for implementing a precision inductive component within a high frequency integrated circuit is disclosed. The inductive component has a structure of multiple conductive layers dielectrically insulated from each other and located above an integrated circuit substrate. The inductive component comprises a spiral-like inductive layer made of a first conductive layer. Additionally, a number of additional ground planes, each patterned out of its own selected conductive layer to minimize an induced eddy current therein thus improving Q (quality factor) under high frequency operation, are employed with either a linear or a rotational offset amongst them to effect a corresponding amount of adjustment of an inductance value of the inductive component. A number of specific design cases are presented with their respective inductance and RF performance parameters.

Abstract: Techniques for integrating multiple transformers are disclosed. Although they can be used in other areas, the techniques are particularly suitable in integrated circuits that are demanded to be of small in size. Several winding configurations of transformers are described and all are designed to not occupy multiple individual silicon spaces that would otherwise be occupied by the multiple transformers. Further, without the multiple individual silicon spaces for the transformers, the parasitic effects that would be otherwise introduced by the transformers in the multiple individual silicon spaces will be minimized. As a result, an integrated circuit chip employing transformers implemented in accordance with one of the techniques can accommodate much higher signal frequency, and have smaller size, thus the cost of the integrated circuit chip can be substantially reduced.

Abstract: It is well known that the parasitic effects in individual components can introduce artifacts into signals when the frequency of the signals exceeds a certain range. Techniques are described to utilize the parasitic effects in favor to the signals by systematically adjusting the components such that the artifacts are minimized. According to one embodiment, a parameter defined as an Electrically Equivalent Geometry or EEG is defined as a function of width and length that confines one part of a transistor controlling how much current can go through. A proper adjustment of the EEG for each of the transistors in a differential amplifier or circuit can reduce the parasitic effects that can cause the artifacts to the signal but also form inherently resonant filtering functions that minimize harmonic components in the output signals.

Abstract: A structure and method for implementing a precision inductive component within a high frequency integrated circuit is disclosed. The inductive component has a structure of multiple conductive layers dielectrically insulated from each other and located above an integrated circuit substrate. The inductive component comprises a spiral-like inductive layer made of a first conductive layer. Additionally, a number of additional ground planes, each patterned out of its own selected conductive layer to minimize an induced eddy current therein thus improving Q (quality factor) under high frequency operation, are employed with either a linear or a rotational offset amongst them to effect a corresponding amount of adjustment of an inductance value of the inductive component. A number of specific design cases are presented with their respective inductance and RF performance parameters.

Abstract: A fundamental building block of 2-level series-gated CML-based CMOS circuit which includes a number of inductive components for an electronic circuit system is disclosed that is capable of driving a significant level of external capacitive load at a high input clock frequency while providing a high level of output signal fidelity for optical data communication. The inductive components can be implemented as either separate inductors or as differentially coupled pairs forming a corresponding transformer element. The value of any particular inductive component is first selected to approximately resonate, at the desired output signal frequency, with its associated equivalent node capacitance but further adjusted to a final value that results in a minimum output waveform distortion for the particular application. Two exemplary cases of application, a Divide-by-2 counter and a Master Slave D-type Flip Flop are presented with associated time domain output waveforms.

Abstract: It is well known that the parasitic effects in individual components can introduce artifacts into signals when the frequency of the signals exceeds a certain range. Techniques are described to utilize the parasitic effects in favor to the signals by systematically adjusting the components such that the artifacts are minimized. According to one embodiment, a parameter defined as an Electrically Equivalent Geometry or EEG is defined as a function of width and length that confines one part of a transistor controlling how much current can go through. A proper adjustment of the EEG for each of the transistors in a differential amplifier or circuit can reduce the parasitic effects that can cause the artifacts to the signal but also form inherently resonant filtering functions that minimize harmonic components in the output signals.

Abstract: A method of designing an electronic circuit system with multiple Field Effect Transistors (FETs) made by a variety of nonstandard industrial processes is presented. With this method, the circuit parameters of the various components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a Silicon On Insulator (SOI) CMOS IC that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The resulting drastic improvement of output signal ripple from each divider stage is graphically presented. In another embodiment, the method is applied to another SOI CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting drastic improvement of output signal ripple is also graphically presented.

Abstract: A D-type latch with current mode switching using MOS transistors for high speed data communication without excessive noise and poor waveform jittering and a method of quantitative circuit design of such D-type latch circuit is presented. With this method, a value of electrically equivalent channel geometry is selected for the input pair of MOS transistors and a different value of electrically equivalent channel geometry is selected for the feedback pair of MOS transistors so as to reduce the resulting amount of output signal ringing as compared to a similar D-type latch circuit where the corresponding values of electrically equivalent channel geometry are equal. Furthermore, a set of output signal waveforms from a divide-by-2 counter and a divide-by-16 counter using the D-type latch as their building block are presented.

Abstract: A method of designing an electronic circuit system with multiple CMOS transistors is presented. With this method, the circuit parameters of the various CMOS transistors as well as the passive electrical components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a CMOS IC (Integrated Circuit) that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The high quality of the resulting output signals from each divider stage is graphically presented. In another embodiment, the method is applied to a CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The high quality of the resulting output signal is also graphically presented.

Abstract: A method of designing an electronic circuit system with multiple Bipolar transistor is presented. With this method, the circuit parameters of the various components of the individual functional building blocks of the system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a Bipolar IC that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The resulting improvement of output signal ripple from each divider stage is graphically presented. In another embodiment, the method is applied to another Bipolar IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting improvement of output signal ripple is also graphically presented.