Abstract: A method for designing a system on a target device includes generating a scheduled netlist and a hardware description language (HDL) of the system from a computer language description of the system. An area report is generated prior to HDL compilation, based on estimates from the scheduled netlist, that identifies resources from the target device required to implement portions of the computer language description of the system.

Abstract: Integrated circuits may be programmed using configuration data to implement desired custom logic circuits. The configuration data may be generated using a logic design system. The logic design system may include first and second compilers and an emulation engine. The first compiler may compile a computer program language description of the logic circuit to generate a hardware description language (HDL) description. The emulation engine may emulate performance of the logic circuit when loaded on a target device and may monitor the emulated performance to generate emulated profile data characterizing the emulated performance of the logic circuit. The first compiler may process the emulated profile data to identify optimizations to perform on the logic circuit and may compile an optimized HDL description. The second compiler may compile optimized configuration data using the optimized HDL.