Patents by Inventor Maryam Shahbazi

Maryam Shahbazi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12174842
    Abstract: There is provided computer-based record identification method, comprising, at a computing device, receiving one or more witness statements relating to an incident, each of the one or more witness statements having a respective first plurality of attributes, each attribute of the first plurality of attributes having a confidence value associated therewith, querying, using the one or more witness statements and the confidence value associated with each of the first plurality of attributes of the one or more witness statements, at least one database having a plurality of event occurrence records stored therein to identify at least one of the plurality of event occurrence records that matches the one or more witness statements, and outputting the at least one of the plurality of event occurrence records.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: December 24, 2024
    Assignee: GENETEC INC.
    Inventors: Louis-Antoine Blais-Morin, Neesha Kodagoda, Helen Kimber, François Séguin, Maryam Shahbazi
  • Publication number: 20240296164
    Abstract: A record identification method comprises, at a computing device having a machine learning model operating therein, obtaining event occurrence record(s) indicative of occurrence of at least one event, each of the event occurrence record(s) having a first plurality of attributes associated therewith, executing the machine learning model to determine a probability distribution of the first plurality of attributes, receiving witness statement(s) relating to an incident, each of the witness statement(s) having a respective second plurality of attributes associated therewith, comparing the probability distribution of the first plurality of attributes to a probability distribution of the respective second plurality of attributes, identifying, based on the comparing, at least one of the event occurrence record(s) for which the probability distribution of the first plurality of attributes matches the probability distribution of the respective second plurality of attributes, and outputting the at least one of the event
    Type: Application
    Filed: April 29, 2024
    Publication date: September 5, 2024
    Inventors: Louis -Antoine BLAIS-MORIN, Neesha KODAGODA, Helen KIMBER, Francois SEGUIN, Maryam SHAHBAZI, Mozhday SHAHBAZI, Maguelonne HERITIER
  • Publication number: 20240184459
    Abstract: Various techniques are provided for selectively operating a memory block in full power or half power modes. In one example, a system comprises a memory block configured to be selectively operated in a full power mode or a half power mode. The memory block comprises an input/output port. The memory block further comprises a first sub-block configured to be powered on during the full power mode and during the half power mode. The memory block further comprises a second sub-block configured to be powered on during the full power mode and powered off during the half power mode. The memory block further comprises routing hardware configured to pass data between the input/output port and the first and second sub-blocks. Additional systems and methods are also provided.
    Type: Application
    Filed: November 29, 2023
    Publication date: June 6, 2024
    Inventors: Maryam Shahbazi, Loren L. McLaury, Bradley A. Sharpe-Geisler
  • Publication number: 20240183902
    Abstract: Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). In one example, a method comprises configuring an intellectual property (IP) block of the PLD to receive a first clock signal and a first data signal at a first component of the IP block, determining a delay associated with the first clock signal between a first input and the first component, configuring a programmable logic cell (PLC) to receive a second clock signal and output the first data signal to the IP block, determining a delay period to synchronize the first clock signal and the first data signal at the first component of the IP block, and configuring an adjustable delay element to apply the delay period to the second clock signal to synchronize the first clock signal and the first data signal at the first component of the IP block.
    Type: Application
    Filed: December 1, 2023
    Publication date: June 6, 2024
    Inventors: Maryam Shahbazi, Bradley A. Sharpe-Geisler, Senani Gunaratna, Loren L. McLaury
  • Publication number: 20240143601
    Abstract: There is provided computer-based record identification method, comprising, at a computing device, receiving one or more witness statements relating to an incident, each of the one or more witness statements having a respective first plurality of attributes, each attribute of the first plurality of attributes having a confidence value associated therewith, querying, using the one or more witness statements and the confidence value associated with each of the first plurality of attributes of the one or more witness statements, at least one database having a plurality of event occurrence records stored therein to identify at least one of the plurality of event occurrence records that matches the one or more witness statements, and outputting the at least one of the plurality of event occurrence records.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Inventors: Louis-Antoine BLAIS-MORIN, Niisha Kodagoda, Helen Kimber, François SÉGUIN, Maryam Shahbazi
  • Publication number: 20160134264
    Abstract: In an integrated circuit, meta-stability prevention circuitry prevents an oscillator, such as a current-controlled oscillator having a ring of differential inverters, from being turned on, for example, during power up, until after the power-supply voltage is sufficiently high for the oscillator ring to achieve oscillation without going into a meta-stable state. In one implementation, a level detector monitors the power-supply voltage level and generates a logic signal indicating whether or not the power-supply voltage level is sufficiently high. That logic signal and a conventional chip-level power-down control signal are applied to logic circuitry that generates control signals for one or more switch transistors that selectively turn on and off the oscillator ring.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Inventors: Maryam Shahbazi, Hamid Ghezel, Ban Pak Wong, Magathi Jayaram