Patents by Inventor Maryse Cournoyer
Maryse Cournoyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11791270Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.Type: GrantFiled: May 10, 2021Date of Patent: October 17, 2023Assignee: International Business Machines CorporationInventors: Kamal K Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, Ravi K. Bonam, Hiroyuki Mori, Yang Liu, Paul S. Andry, Isabel De Sousa
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Publication number: 20220359401Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.Type: ApplicationFiled: May 10, 2021Publication date: November 10, 2022Inventors: Kamal K. Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, RAVI K. BONAM, HIROYUKI MORI, Yang Liu, Paul S. Andry, Isabel De Sousa
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Patent number: 11209598Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.Type: GrantFiled: February 28, 2019Date of Patent: December 28, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Barnim Alexander Janta-Polczynski, Isabel De Sousa, Jean Audet, Maryse Cournoyer, Sylvain Pharand, Roxan Lemire, Louis-Marie Achard, Paul Francis Fortier
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Patent number: 11177217Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.Type: GrantFiled: January 9, 2020Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
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Patent number: 11139269Abstract: An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.Type: GrantFiled: January 25, 2020Date of Patent: October 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamal K. Sikka, Paul S. Andry, Yang Liu, Pascale Gagnon, Christian Bergeron, Maryse Cournoyer
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Publication number: 20210233892Abstract: An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.Type: ApplicationFiled: January 25, 2020Publication date: July 29, 2021Inventors: Kamal K. Sikka, Paul S. Andry, Yang Liu, Pascale Gagnon, Christian Bergeron, Maryse Cournoyer
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Patent number: 10991635Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.Type: GrantFiled: July 20, 2019Date of Patent: April 27, 2021Assignee: International Business Machines CorporationInventors: Dale Curtis McHerron, Kamal K. Sikka, Joshua M. Rubin, Ravi K. Bonam, Ramachandra Divakaruni, William J. Starke, Maryse Cournoyer
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Patent number: 10784202Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.Type: GrantFiled: December 1, 2017Date of Patent: September 22, 2020Assignee: International Business Machines CorporationInventors: Francois Arguin, Luc Guerin, Maryse Cournoyer, Steve E. Whitehead, Jean Audet, Richard D. Langlois, Christian Bergeron, Pascale Gagnon, Nathalie Meunier
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Publication number: 20200279840Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.Type: ApplicationFiled: February 28, 2019Publication date: September 3, 2020Inventors: BARNIM ALEXANDER JANTA-POLCZYNSKI, Isabel De Sousa, Jean Audet, Maryse Cournoyer, Sylvain Pharand, Roxan Lemire, Louis-Marie Achard, Paul Francis Fortier
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Publication number: 20200144187Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.Type: ApplicationFiled: January 9, 2020Publication date: May 7, 2020Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
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Patent number: 10580738Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.Type: GrantFiled: March 20, 2018Date of Patent: March 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
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Publication number: 20190295952Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.Type: ApplicationFiled: March 20, 2018Publication date: September 26, 2019Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
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Publication number: 20190172787Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.Type: ApplicationFiled: December 1, 2017Publication date: June 6, 2019Inventors: Francois Arguin, Luc Guerin, Maryse Cournoyer, Steve E. Whitehead, Jean Audet, Richard D. Langlois, Christian Bergeron, Pascale Gagnon, Nathalie Meunier