Patents by Inventor Maryse Paoli

Maryse Paoli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fabrication processes for semiconductor non-volatile memory device
    Patent number: 6642108
    Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: November 4, 2003
    Assignee: STMicroelectronics SA
    Inventors: Thomas Skotnicki, Didier Dutartre, Pascal Ribot, Maryse Paoli, Richard Fournel
  • Fabrication processes for semiconductor non-volatile memory device
    Publication number: 20030038315
    Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.
    Type: Application
    Filed: October 18, 2002
    Publication date: February 27, 2003
    Applicant: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Didier Dutartre, Pascal Ribot, Maryse Paoli, Richard Fournel
  • Method of correcting topographical effects on a micro-electronic substrate
    Patent number: 6387808
    Abstract: A method of correcting topographical effects on a microelectronic substrate, the method comprising the steps consisting in depositing a layer of resin on the structure to be planarized having topography in relief surrounded by isolation zones, and subjecting said resin layer in its zones superposed on underlying zones of high topographical density to photolithography by means of a mask possessing a standard mesh without any one-to-one coincidence with the underlying topography.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: May 14, 2002
    Assignee: France Telecom
    Inventors: André Schiltz, Maryse Paoli, Patrick Schiavone, Alain Prola
  • Semiconductor non-volatile memory device and corresponding fabrication process
    Publication number: 20010050387
    Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.
    Type: Application
    Filed: March 21, 2001
    Publication date: December 13, 2001
    Applicant: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Didier Dutartre, Pascal Ribot, Maryse Paoli, Richard Fournel
  • Method of isolating active areas of a semiconductor substrate by shallow trenches and narrow trenches
    Patent number: 5641704
    Abstract: The semiconductor device includes in a semiconductor substrate (1) at least one predetermined region (6) of the substrate intended subsequently to form an active area, uncovered on its upper surface and situated between lateral trenches (7) containing an insulative material including a layer (9) of a planarising first oxide and at least one underlying layer (8) of a conformal second oxide. The insulative material can form on either side of said uncovered predetermined region (6) of the substrate a boss (16) on the plane upper surface of the device (D) less than 1000 .ANG. high.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: June 24, 1997
    Assignee: France Telecom
    Inventors: Maryse Paoli, Pierre Brouquet, Michel Haond
  • Method of and device for isolating active areas of a semiconducor substrate by quasi-plane shallow trenches
    Patent number: 5604149
    Abstract: The semiconductor device comprises in a semiconductor substrate (1) at least one predetermined region (6) of the substrate intended subsequently to form an active area, uncovered on its upper surface and situated between the lateral trenches (7) containing an insulative material including at least one layer of a conformal oxide, the insulative material forming on either side of said uncovered predetermined region of the substrate a boss (16) on the plane upper surface of the device. The height of the boss is less than 1 000 .ANG. and the insulative material can also include planarising oxide.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: February 18, 1997
    Assignee: France Telecom
    Inventors: Maryse Paoli, Pierre Brouquet, Michel Haond