Abstract: Disclosed herein are systems, methods, and computer-readable media for sorting datasets within a Processing in Memory (PIM)-based system. A request to sort a dataset stored in a 3D-stacked memory can be received. The request can identify a specific dataset and sorting criteria, which includes a plurality of keys. The dataset can be partitioned into several subarrays across various memory banks within the 3D-stacked memory. Each piece of data within these subarrays can be separated into buckets based on the keys. Local histograms for each subarray and bank histograms based on the local histograms can be generated. A prefix-sum operation on the bank histograms can determine individual positions for the sorted dataset. Aggregation of the subarrays from all memory banks can form the sorted dataset, which can be subsequently returned.

Abstract: An integrated circuit memory device can include a plurality of banks of memory, each of the banks of memory including a first pair of sub-arrays comprising first and second sub-arrays, the first pair of sub-arrays configured to store data in memory cells of the first pair of sub-arrays, a first row buffer memory circuit located in the integrated circuit memory device adjacent to the first pair of sub-arrays and configured to store first row data received from the first pair of sub-arrays and configured to transfer the row data into and/or out of the first row buffer memory circuit, and a first sub-array level processor circuit in the integrated circuit memory device adjacent to the first pair of sub-arrays and operatively coupled to the first row data, wherein the first sub-array level processor circuit is configured to perform column oriented processing a sparse matrix kernel stored, at least in-part, in the first pair of sub-arrays, with input vector values stored, at least in part, in the first pair of sub

Abstract: Apparatus includes a plurality of memory cells (e.g., a dynamic random access memory (DRAM)) addressable as rows and columns and a plurality of matching circuits configured to be coupled to respective bit lines associated with the columns A control circuit is configured to store respective reference sequences (e.g., binary-encoded k-mer patterns) in respective ones of the columns, to sequentially provide rows of bits stored in the memory cells and bits of a query to the matching circuits, and to identify one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits.

Abstract: Apparatus includes a plurality of memory cells (e.g., a dynamic random access memory (DRAM)) addressable as rows and columns and a plurality of matching circuits configured to be coupled to respective bit lines associated with the columns A control circuit is configured to store respective reference sequences (e.g., binary-encoded k-mer patterns) in respective ones of the columns, to sequentially provide rows of bits stored in the memory cells and bits of a query to the matching circuits, and to identify one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits.

Abstract: A method of processing data in a memory can include accessing an array of memory cells located on a semiconductor memory die to provide a row of data including n bits, latching the n bits in one or more row buffer circuits adjacent to the array of memory cells on the semiconductor memory die to provide latched n bits operatively coupled to a column address selection circuit on the semiconductor memory die to provide a portion of the n latched bits as data output from the semiconductor memory die responsive to a memory read operation, and serially transferring the latched n bits in the row buffer circuit to an arithmetic logic unit (ALU) circuit located adjacent to the row buffer circuit on the semiconductor memory die.

Abstract: A method of processing data in a memory can include accessing an array of memory cells located on a semiconductor memory die to provide a row of data including n bits, latching the n bits in one or more row buffer circuits adjacent to the array of memory cells on the semiconductor memory die to provide latched n bits operatively coupled to a column address selection circuit on the semiconductor memory die to provide a portion of the n latched bits as data output from the semiconductor memory die responsive to a memory read operation, and serially transferring the latched n bits in the row buffer circuit to an arithmetic logic unit (ALU) circuit located adjacent to the row buffer circuit on the semiconductor memory die.